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From: David Tweed on 2 Dec 2005 08:19
dp wrote:
> If the purpose is to have the FIFO (and not to build it, say,
> for learning or economic purposes), you can use one of
> the 72XX (IDT used to make them) FIFO chips. They have
> the R/W pointer circuitry inside etc., really convenient
> to use - and you will need no memory address lines out
> of the FPGA, nor will the data necessarily go through it
> (that is, you can just handle the full/empty flags and
> the R/W strobes - and there also is a half full flag).

Yes, but they are of limited size and rather expensive.

I once needed to delay a T1/E1 signal (all three states,
so 1.544 or 2.048 million bit-pairs per second) by up to
tens of milliseconds, continuously adjustable. I ended up
with an external cheap generic CMOS SRAM (128K x 8) and
an Actel ACT2 FPGA to control it. Most of the FPGA runs
synchronously with the output clock at 4x the data rate
(6.176 or 8.192 MHz). For the input data, there's a 4 x 2
shift register that runs at the input clock rate and a
block of logic that passes memory write requests to the
output clock domain.

With 16 clocks per read/write pair, there was plenty of
time to work with and resolve conflicts between reads and
writes. I even did all of the address arithmetic using a
2-bit wide serial data path to save logic.

-- Dave Tweed
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