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From: rickman on 1 Mar 2010 19:44
On Mar 1, 7:11 pm, -jg <jim.granvi...(a)gmail.com> wrote:
> On Mar 2, 12:56 pm, rickman <gnu...(a)gmail.com> wrote:
>
> > It clearly shows a quick rise time (~1 ns) to a level lower
> > than Vdd because of the 100 ohm load to ground.  But after about 2-3
> > ns the voltage drops off and remains constant for the duration of the
> > 20 ns data sample.  I am pretty sure you can't generate this waveform
> > with a simple RLC model.  It also makes me suspicious of the entire
> > IBIS file thing.  
>
> Yes, that sounds simply broken. Like the sim-engine,
> and the model got out of step.
> Did your scope 'reality check' look anything like that?

The "sim-engine" is just a display of the contents of the V-t curve
given in the model. I found it in the file and the data is exactly
like the curve drawn.


> > It just seems like this is a very poor way to model
> > an I/O, but then I haven't looked at it in detail.
>
> IBIS is simplified output from the 'real spice'.
> So they just have single numbers for ramp rates, and
> a table plot for I-V.
>
>  Given the limits of the information in the IBIS, you should still be
> able to get useful spice data points.
>  Certainly more than enough, to correlate with bench measurements, and
> for clock ringing (which is what you were looking for).
>
> Tho I'm not sure I'd try and get Eye patterns from it ;)
> It's  best to use Hyperlynx for that level of analysis.

What the heck do you feed into Hyperlynx? That is what the IBIS
models are supposed to be for from what I have read. Hyperlynx is not
spice, it uses the IBIS models for the drivers and inputs and it gets
info on your pcb from your layout package. All in all, it is a *very*
expensive way to design high speed PCBs and like I said, I didn't find
it produced very good results.


>  Those spice examples look quite plausible to me.
> Both show ringing, but with (expected) quite different amplitudes and
> phases.

In the end we picked a 12 mA, FAST output which gives a 6 ns rise time
with a small wiggle in the rising edge at around 2.6 volts pretty well
above the typical threshold. With an 8 mA drive the rise time is
slower and the wiggle shows up further down in the curve near the
threshold. The common factor is a ~4 ns time delay which matches the
end of the initial pulse in the V-t curve data. I don't think any of
this is ringing due to reflections in the trace. A 6 ns rise time
would require a trace a foot or more long to create any noticeable
reflection. The trace on this board is maybe 3 inches long total. I
don't know what the IBIS data is about.

Rick
From: -jg on 1 Mar 2010 20:37
On Mar 2, 1:44 pm, rickman <gnu...(a)gmail.com> wrote:
> On Mar 1, 7:11 pm, -jg <jim.granvi...(a)gmail.com> wrote:
>
>
> What the heck do you feed into Hyperlynx?  That is what the IBIS
> models are supposed to be for from what I have read.  Hyperlynx is not
> spice, it uses the IBIS models for the drivers and inputs and it gets
> info on your pcb from your layout package.  All in all, it is a *very*
> expensive way to design high speed PCBs and like I said, I didn't find
> it produced very good results.

The top end Hyperlynx products, include the trace parasitics, and
lossy transmission line models. So if you are serious about eye
patterns, they are a good idea.
If you just want ringing/drive selector, then yes, they could be an
overkill.

Hence the spice alternative.


>
> In the end we picked a 12 mA, FAST output which gives a 6 ns rise time
> with a small wiggle in the rising edge at around 2.6 volts pretty well
> above the typical threshold.  With an 8 mA drive the rise time is
> slower and the wiggle shows up further down in the curve near the
> threshold.  The common factor is a ~4 ns time delay which matches the
> end of the initial pulse in the V-t curve data.  I don't think any of
> this is ringing due to reflections in the trace.  A 6 ns rise time
> would require a trace a foot or more long to create any noticeable
> reflection.  The trace on this board is maybe 3 inches long total.  I
> don't know what the IBIS data is about.

I used 22nH, and 5pF as the load, and got noticable ringing effects,
with fast-ish edges.

That ~3 inch trace will be 30-40nH, and rather more than 5pF, so your
slower edges should give similar results.

Try it and see :)

-jg



From: rickman on 2 Mar 2010 00:15
On Mar 1, 8:37 pm, -jg <jim.granvi...(a)gmail.com> wrote:
> On Mar 2, 1:44 pm, rickman <gnu...(a)gmail.com> wrote:
>
> > On Mar 1, 7:11 pm, -jg <jim.granvi...(a)gmail.com> wrote:
>
> > What the heck do you feed into Hyperlynx?  That is what the IBIS
> > models are supposed to be for from what I have read.  Hyperlynx is not
> > spice, it uses the IBIS models for the drivers and inputs and it gets
> > info on your pcb from your layout package.  All in all, it is a *very*
> > expensive way to design high speed PCBs and like I said, I didn't find
> > it produced very good results.
>
>  The top end Hyperlynx products, include the trace parasitics, and
> lossy transmission line models. So if you are serious about eye
> patterns, they are a good idea.
>  If you just want ringing/drive selector, then yes, they could be an
> overkill.
>
>  Hence the spice alternative.
>
>
>
> > In the end we picked a 12 mA, FAST output which gives a 6 ns rise time
> > with a small wiggle in the rising edge at around 2.6 volts pretty well
> > above the typical threshold.  With an 8 mA drive the rise time is
> > slower and the wiggle shows up further down in the curve near the
> > threshold.  The common factor is a ~4 ns time delay which matches the
> > end of the initial pulse in the V-t curve data.  I don't think any of
> > this is ringing due to reflections in the trace.  A 6 ns rise time
> > would require a trace a foot or more long to create any noticeable
> > reflection.  The trace on this board is maybe 3 inches long total.  I
> > don't know what the IBIS data is about.
>
>  I used 22nH, and 5pF as the load, and got noticable ringing effects,
> with fast-ish edges.
>
>  That ~3 inch trace will be 30-40nH, and rather more than 5pF, so your
> slower edges should give similar results.
>
>  Try it and see :)
>
>  -jg

I'm talking about the boards. I get virtually no ringing with the
slower edge rates. The fastest, 20 mA/FAST, setting gives pronounced
ringing and 16 mA has some as well. They are both 2 ns or less rise
times. At 12 ns the ringing is gone and I only see the tiny notch in
the rising edge that I am convinced is not ringing or reflection.
BTW, a transmission line does not ring. You can get reflections, but
unless there is some sort of feedback in your IO driver that is
oscillating, you won't see true ringing with a transmission line...
unless there is something with transmission lines that I didn't
learn. It is often that reflections look like ringing because they
echo several times at lower amplitude each time around. No?

Rick
From: -jg on 2 Mar 2010 01:08
On Mar 2, 6:15 pm, rickman <gnu...(a)gmail.com> wrote:
>
> I'm talking about the boards.  I get virtually no ringing with the
> slower edge rates.  The fastest, 20 mA/FAST, setting gives pronounced
> ringing and 16 mA has some as well.  They are both 2 ns or less rise
> times.  At 12 ns the ringing is gone and I only see the tiny notch in
> the rising edge that I am convinced is not ringing or reflection.

It depends on your terminology.
The notch I mention below, I would call ringing, as it
comes from a LCR+Slope model. It is effectively ringing summed onto
the slowish rise time, and is not huge, but large enough to see a
slight reverse in voltage.

> BTW, a transmission line does not ring.  You can get reflections, but
> unless there is some sort of feedback in your IO driver that is
> oscillating, you won't see true ringing with a transmission line...
> unless there is something with transmission lines that I didn't
> learn.  It is often that reflections look like ringing because they
> echo several times at lower amplitude each time around.  No?
>
> Rick

Just for fun, I added some guestimate numbers from what you said, and
added a probe to the driving end, and voila, guess what?

A small notch appears, on the driving end ;)

Which end were you probing, your end, or connector, or the customers
FPGA pin ?

-jg
From: Kim Enkovaara on 2 Mar 2010 05:37
rickman wrote:

> What the heck do you feed into Hyperlynx? That is what the IBIS
> models are supposed to be for from what I have read. Hyperlynx is not
> spice, it uses the IBIS models for the drivers and inputs and it gets
> info on your pcb from your layout package. All in all, it is a *very*
> expensive way to design high speed PCBs and like I said, I didn't find
> it produced very good results.

Hyperlynx also can use spice (hspice or eldo) models, so you can use a
mixture of ibis and spice models for the simulation. And I think also
AMS and IBIS-AMI is supported.

And also the trace models do not have to come from the layout. I have
used the tool often for design exploration. For example checking the
termination schemes (ODT vs. separate resistors etc.) and the results
have matched quite well to the real world. Altough the trace was only
based on PCB stackup model, vias and trace lengths on different layers.

--Kim
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