Summing with carry problems ...
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From: Kappa on 8 Apr 2010 11:54 > Does total(4) get used anywhere? If not, then it will get optimized > away since it is not needed. Yes, I use all 5 bits of "total" signal. > You tell us, the use of total(4) would be in your code. Any signal > that does cause an output pin to change either directly, or > indirectly, will get optimized away. OK, but I use all signal ... secureasm
From: Kappa on 8 Apr 2010 12:04 Hi, I have resolved my problem. This code not work : ############# [CODE]############# signal E : std_logic_vector (3 downto 0); signal Z : std_logic_vector (3 downto 0); signal r : std_logic; signal total : std_logic_vector(4 downto 0); total <= Zi + Ei + r; ############# [/CODE]############# This code work very well : ############# [CODE]############# signal E : std_logic_vector (3 downto 0); signal Z : std_logic_vector (3 downto 0); signal r : std_logic; signal total : integer; signal total_signal : std_logic_vector(4 downto 0); total <= conv_integer(Zi) + conv_integer(Ei) + conv_integer(r); total_signal <= conv_std_logic_vector(total, 5); ############# [/CODE]############# This create adder with carry out signal ... Thanks. secureasm
From: Symon on 8 Apr 2010 19:41
On 4/8/2010 5:04 PM, Kappa wrote: > Hi, I have resolved my problem. > This code work very well : > secureasm It work very well until next time. Stop, in the name of your sanity, using std_logic_arith. Read, as a matter of some urgency, http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf You should never mix your arithmetic libraries!* numeric_std is all you need. Cheers, Syms. * http://www.youtube.com/watch?v=Qg77BCUi0pM |