From: maxascent on 15 Jan 2010 10:52 >Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will >that be okay? I wouldnt of thought that version of Modelsim will work. Jon --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: Jonathan Bromley on 15 Jan 2010 11:24 On Fri, 15 Jan 2010 07:32:13 -0800 (PST), jjlindula wrote: [me] >> using SystemVerilog's object-oriented programming features, >> and those definitely require top-end features of the simulator >> that you simply won't get in the cheaper or "student" editions. [you] >Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will >that be okay? I'm afraid not. You will probably find that quite a few of the SV design features are fully supported in that version - interfaces, always_comb, structs, .* port connection, that sort of thing - but I would be astonished if you had access to any of the big-ticket verification stuff such as classes and randomization. To find out, try these little examples. Be sure to give the files ".sv" extension, or alternatively use the -sv compile option to the vlog command. <example 1> module enum_test; // probably works OK typedef enum {first, second, third} ordinal; ordinal which; initial begin which = second; $display("this should print 'second': %s", which.name()); end endmodule <example 2> module random_test; // I don't expect this to work in MSim AE integer i, ok; initial begin repeat (10) begin ok = randomize(i) with {i inside {1,2,4,8,16};}; if (ok) $display("random value is %0d", i); else $display("randomization FAILED"); end end endmodule <example 3> module struct_test; // this probably OK typedef struct {int a; bit b;} s_ab; s_ab ab; initial begin ab = '{15, 0}; $display("ab.a should be 15: %0d", ab.a); $display("ab.b should be 0: %0d", ab.b); end endmodule <example 4> module string_test; // not sure about this one string s1, s2; int i; initial begin s1 = "hello"; i = 7; $sformat(s2, "%s, i=%0d", s1, i); $display("Should print 'hello, i=7': %s", s2); $display("The word 'hello' has %0d characters", s1.len()); end endmodule <example 5> module class_test; // no chance of this working! class C; int a; string name; function new(string n = "unnamed", int v=0); name = n; a = v; endfunction function void print(); $display("%s.a=%0d", name, a); endfunction endclass initial begin C c1 = new; C c2 = new("c2", 5); $display("Next line should say unnamed.a=0"); c1.print(); $display("Next line should say c2.a=5"); c2.print(); end endmodule All these examples run just fine in the full version. -- Jonathan Bromley
From: Mark Curry on 15 Jan 2010 11:47 In article <oi51l5dco9u5ncgo207pg8s8s4g6b0mb83(a)4ax.com>, Jonathan Bromley <jonathan.bromley(a)MYCOMPANY.com> wrote: >On Fri, 15 Jan 2010 07:32:13 -0800 (PST), jjlindula wrote: > >[me] >>> using SystemVerilog's object-oriented programming features, >>> and those definitely require top-end features of the simulator >>> that you simply won't get in the cheaper or "student" editions. > >[you] >>Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will >>that be okay? > >I'm afraid not. > >You will probably find that quite a few of the SV design features >are fully supported in that version - interfaces, always_comb, >structs, .* port connection, that sort of thing - but I would >be astonished if you had access to any of the big-ticket >verification stuff such as classes and randomization. To >find out, try these little examples. Be sure to give the >files ".sv" extension, or alternatively use the -sv compile >option to the vlog command. > <snipped (good!) examples> Actually, modelsim SE supports a large set of SystemVerilog. All the examples work except for example 2 with Modelsim SE. SE supports all of the "design" features of SystemVerilog as well as SystemVerilog classes. You need Questa for the constraint solver and SystemVerilog Assertions. Which makes sense as that's the harder problem to solve for tool vendors. Now, I'm using SE - which is NOT a "Starter Edition" as the OP indicated. I thought the starter product was "DE" or something like that. Your mileage may vary - Mentor likes to slice and dice their product definition / licensing to (confusing) extremes... --Mark
From: Nial Stewart on 15 Jan 2010 12:13 > Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will > that be okay? As the others have said probably not. The OEM /Starter Editions are all knobbled a bit, they run at reduced speed or functionality. The base 'normal' spec of Modelsim is PE (Properly Expensive), this is superceded by SE (Specially Expensive). [Particularly here in the UK where tools prices seem to be the same in � as the guys from the States get them in $ (�1 ~ $1.6)] Nial.
From: HT-Lab on 15 Jan 2010 13:14 "Mark Curry" <gtwrek(a)sonic.net> wrote in message news:4b509c09$0$1597$742ec2ed(a)news.sonic.net... > In article <oi51l5dco9u5ncgo207pg8s8s4g6b0mb83(a)4ax.com>, > Jonathan Bromley <jonathan.bromley(a)MYCOMPANY.com> wrote: >>On Fri, 15 Jan 2010 07:32:13 -0800 (PST), jjlindula wrote: >> >>[me] >>>> using SystemVerilog's object-oriented programming features, >>>> and those definitely require top-end features of the simulator >>>> that you simply won't get in the cheaper or "student" editions. >> >>[you] >>>Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will >>>that be okay? >> >>I'm afraid not. >> >>You will probably find that quite a few of the SV design features >>are fully supported in that version - interfaces, always_comb, >>structs, .* port connection, that sort of thing - but I would >>be astonished if you had access to any of the big-ticket >>verification stuff such as classes and randomization. To >>find out, try these little examples. Be sure to give the >>files ".sv" extension, or alternatively use the -sv compile >>option to the vlog command. >> > <snipped (good!) examples> > > Actually, modelsim SE supports a large set of SystemVerilog. > All the examples work except for example 2 with > Modelsim SE. SE supports all of the "design" features > of SystemVerilog as well as SystemVerilog classes. > You need Questa for the constraint solver and SystemVerilog > Assertions. SVA (and PSL) are supported in Modelsim DE (much cheaper than SE/Questa and it runs under Linux :-), but you are correct regarding the rest. Hans www.ht-lab.com > Which makes sense as that's the harder > problem to solve for tool vendors. > > Now, I'm using SE - which is NOT a "Starter Edition" as the OP indicated. > I thought the starter product was "DE" or something like that. > > Your mileage may vary - Mentor likes to slice and dice their > product definition / licensing to (confusing) extremes... > > --Mark >
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