From: HT-Lab on 15 Jan 2010 13:21 "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in message news:7rbm1tFrl4U1(a)mid.individual.net... >> Thanks Jonathan, I'm using Modelsim Altera Starter Edition 6.5b, will >> that be okay? > > As the others have said probably not. > > The OEM /Starter Editions are all knobbled a bit, they run at reduced > speed or functionality. > > The base 'normal' spec of Modelsim is PE (Properly Expensive), this is > superceded by SE (Specially Expensive). :-) > > > [Particularly here in the UK where tools prices seem to be the same in � > as the guys from the States get them in $ (�1 ~ $1.6)] That is indeed very annoying, Mentor is not the only one doing it. http://www.amanwithapencil.com/adobe.html Hans www.ht-lab.com > > > > Nial. >
From: Anssi Saari on 15 Jan 2010 17:40 Jonathan Bromley <jonathan.bromley(a)MYCOMPANY.com> writes: > You will probably find that quite a few of the SV design features > are fully supported in that version - interfaces, always_comb, > structs, .* port connection, that sort of thing - but I would > be astonished if you had access to any of the big-ticket > verification stuff such as classes and randomization. To > find out, try these little examples. Be sure to give the > files ".sv" extension, or alternatively use the -sv compile > option to the vlog command. Well, since all I have at home is the Altera free edition and in fact it seems it's the only free Modelsim out for Linux right now (well, Actel has a 45 day trial), I tried these out. Only example complains about missing support: Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009 -- Compiling module random_test ** Warning: ex2.sv(5): (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. And trying to run it gives: # vsim random_test # Loading sv_std.std # Loading work.random_test VSIM 3> run -all # ** Fatal: ex2.sv(5): Unable to check out verification license for randomize() feature. # Time: 0 ps Iteration: 0 Process: /random_test/#INITIAL#3 File: ex2.sv # Fatal error in Module random_test at ex2.sv line 5 # # HDL call sequence: # Stopped at ex2.sv 5 Module random_test But all the others work. Not bad for a freebie...
From: jjlindula on 15 Jan 2010 19:39 On Jan 15, 2:40 pm, Anssi Saari <a...(a)sci.fi> wrote: > Jonathan Bromley <jonathan.brom...(a)MYCOMPANY.com> writes: > > You will probably find that quite a few of the SV design features > > are fully supported in that version - interfaces, always_comb, > > structs, .* port connection, that sort of thing - but I would > > be astonished if you had access to any of the big-ticket > > verification stuff such as classes and randomization. To > > find out, try these little examples. Be sure to give the > > files ".sv" extension, or alternatively use the -sv compile > > option to the vlog command. > > Well, since all I have at home is the Altera free edition and in fact > it seems it's the only free Modelsim out for Linux right now (well, > Actel has a 45 day trial), I tried these out. Only example complains > about missing support: > > Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009 > -- Compiling module random_test > ** Warning: ex2.sv(5): (vlog-2186) SystemVerilog testbench feature > (randomization, coverage or assertion) detected in the design. > These features are only supported in Questasim. > > And trying to run it gives: > > # vsim random_test > # Loading sv_std.std > # Loading work.random_test > VSIM 3> run -all > # ** Fatal: ex2.sv(5): Unable to check out verification license for randomize() feature. > # Time: 0 ps Iteration: 0 Process: /random_test/#INITIAL#3 File: ex2.sv > # Fatal error in Module random_test at ex2.sv line 5 > # > # HDL call sequence: > # Stopped at ex2.sv 5 Module random_test > > But all the others work. Not bad for a freebie... Thanks everyone for your input. My question is relating to the cost of a simulator that supports SystemVerilog Verfication, just how much should I expect to spend for one license? If its too expensive I'll have to stick with sytem testbenches. joe
From: Petter Gustad on 17 Jan 2010 15:12 "jjlindula(a)hotmail.com" <jjlindula(a)hotmail.com> writes: > Thanks everyone for your input. My question is relating to the cost of > a simulator that supports SystemVerilog Verfication, just how much > should I expect to spend for one license? If its too expensive I'll > have to stick with sytem testbenches. If you have to ask you can't afford it... Anyway you should check with Mentor, maybe they can give you a deal. I've never used Questa myself, only Synopsys VCS. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
From: Charles Gardiner on 18 Jan 2010 05:50 > Thanks everyone for your input. My question is relating to the cost of > a simulator that supports SystemVerilog Verfication, just how much > should I expect to spend for one license? If its too expensive I'll > have to stick with sytem testbenches. > > joe To put a ball park on it, about the price of a relatively well-equiped medium range car ;). If you get a great deal from Aldec / Cadence / Mentor / Synopsys, maybe the price of a well equiped small car.
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