Tabula. (FPGA start up)
in [FPGA]
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From: rickman on 4 Mar 2010 18:40 On Mar 2, 4:28 pm, -jg <jim.granvi...(a)gmail.com> wrote: > On Mar 3, 12:22 am, Symon <symon_bre...(a)hotmail.com> wrote: > > > This lot seems to be revealing a bit more about their stuff. > > >http://www.mercurynews.com/breaking-news/ci_14493616 > > >http://www.tabula.com > > Time will tell.... > > meanwhile, over in the other corners, anyone remember Triscend ? > > Well, others are having a crack at the same market, but > slightly updated, for 2010. > > See Cypress PSoC5 (Data, no open samples yet) and the just unveiled > Actel A2F200 (supposedly real silicon & Eval) > > These both bundle a FLASH Cortex uC with Analog and FPGA fabric. > > Sounds great on a marketing-lunch-napkin, but the fish-hook in this > has always been price, and the conflict of constrain of > Flash.Ram.cells. > > The sampling smaller sibling, the PSoC3 has moved to ~$20 in price > indicators, and the A2F200 is showing ~$40 (no indications yet of the > A2F060) > > You can get a choice of ARM core, for $1-$3, and a choice of CPLD- > FPGA for $3-$6, so that single-package-premium really narrows down the > customers. > > -jg Yeah, I have been watching the Cypress stuff and I am not overly impressed. I guess the new stuff far outdoes the PSOC1, but at those prices they are addressing a totally different market and likely will only find a home in very space constrained designs. I just heard about the Actel parts and they seem interesting. But I bet they bring a seriously painful price. That will be the determiner. The PSOC3/5 and Actel SmartFusion parts are also very different in size with Actel SmartFusion coming in a 256 BGA at the smallest and the PSOC3/5 a 100 pin package at the largest IIRC. Other FPGAs don't do analog so well, but they can be used with a soft processor to compete with the low end of these parts. Rick Rick
From: rickman on 4 Mar 2010 18:43 On Mar 2, 8:03 pm, -jg <jim.granvi...(a)gmail.com> wrote: > On Mar 3, 12:22 am, Symon <symon_bre...(a)hotmail.com> wrote: > > > This lot seems to be revealing a bit more about their stuff. > > >http://www.mercurynews.com/breaking-news/ci_14493616 > > A better overview is herehttp://www.eetasia.com/ART_8800599499_499495_NT_b33fb563_2.HTM > > Some of what Tabula say, reads more like a patent dance, than any > technical explanation. > > So, it is locally 1.6GHz, with time-sliced threads. > It might save Logic and routing, but it will have no config-memory > saving, and it ADDS the complexity of > rapid config multiplex. (not to mention power impacts) > > We already have Achronix climing 1.5GHz PLDs since 2008, and XMOS > have 400-500Mhz hard-time-sliced cores shipping also. > > Tabula have some rather quaint terminology, as they try to spin what > they do, but designers have always tried to do more serially & > pipeline, to save resource, if they can. > > It seems their SW will do the 'thread slice & dice' for you, and that > may be the critical point. > > If that works, and you can debug it, it could be useful. If it fails, > it will fail in a tangle. > > -jg Yeah, a lot of their success will depend on the tools. Not only do they need to work, they need to be usable. I am trying to think how to write VHDL for hardware that really is sequential as well as concurrent. Rick
From: -jg on 4 Mar 2010 19:22 On Mar 5, 12:43 pm, rickman <gnu...(a)gmail.com> wrote: > On Mar 2, 8:03 pm, -jg <jim.granvi...(a)gmail.com> wrote: > > > It seems their SW will do the 'thread slice & dice' for you, and that > > may be the critical point. > > > If that works, and you can debug it, it could be useful. If it fails, > > it will fail in a tangle. > > > -jg > > Yeah, a lot of their success will depend on the tools. Not only do they need to work, they need to be usable. I am trying to think how to write VHDL for hardware that really is sequential as well as concurrent. > > Rick I'm exercising the XMOS devices currently, and they are certainly interesting devices. They have a truly hard/deterministic threaded core and some quite good tools. Sadly, the Docs are scattered and read like an in-joke. (and on a device as left-field as XMOS, knowing what it can & can't do, is important) I am currently seeing if a design that is CPLD+RAM, can work on XMOS. RAM in there is easy, (way more than any similar priced CPLD/FPGA) but hitting the speed targets in SW, is 'interesting', but by careful slice into threads, it might just make it. 4 threads come at zero speed cost, as do 32 bit datapaths. Tabula's approach seems a morph of this. It should work well on code that needs to be hard-deterministic, and that can serialize nicely to shrink logic. Something like Base-station math-ops would be a good market footprint, and it is unlikely to be low power. Memory&bandwidths will be the other key factors. -jg
From: Symon on 4 Mar 2010 19:29 On 3/4/2010 12:46 PM, Eric Smith wrote: > time they ship product. Successful startups usually have something > that is *many* times better than the existing products, on some axis > almost entirely orthogonal to the prior metrics. > > Eric Mate, Ever wonder if you've been doing this too long? Did you write that last phrase with a straight face? Cheers, Syms.
From: Symon on 4 Mar 2010 19:31
On 3/4/2010 11:06 PM, rickman wrote: > to actually make an impact in the market. Intel may keep them around > just to keep the FTC off their aggressive and illegal pricing backs. > > Rick Yep. http://www.theregister.co.uk/2009/11/18/amd_to_pay_down_debt/ |