core memory
in [Design]
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From: John Larkin on 7 Dec 2009 23:15 On Mon, 07 Dec 2009 21:45:07 +0200, Paul Keinanen <keinanen(a)sci.fi> wrote: >On Mon, 7 Dec 2009 14:11:00 -0000, "TTman" <someone.pc(a)ntlworld.com> >wrote: > >> >>"John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message >>news:kqalh59i8jsogn1t6p3ghuaop5c137qtoj(a)4ax.com... >>> Testing some FTP stuff, threw up some test files... >>> >>> ftp://jjlarkin.lmi.net/Core_304bits.jpg >>> >>> ftp://jjlarkin.lmi.net/Core_4K.jpg >>> >>> ftp://jjlarkin.lmi.net/Core_4Kdetail.jpg >>> >>> John >>> >>> >>I remember using those back in the early 70s. Made in Ireland.... 16K and >>32K, but I forget the width. It was for a PDP 'clone' that was designed by >>some Ex Uni boffins from Sussex. Controller board was a nightmare ( as I >>remember), full of 121 and 123 monostables :( > > >Do you have more details about these clones ? > >The only PDP-11 clones that I am aware of are the Russian SM4 >(PDP-11/34 clone) and the E60 (LSI-11/03 clone). > There were at least two pre-Mentec PDP-11 clones made in the USA. One was commercial and unauthorized, one aerospace and apparently blessed by DEC. I can't recall the names. John
From: GregS on 8 Dec 2009 09:33 In article <7o4oviF3o5qq0U6(a)mid.individual.net>, Dirk Bruere at NeoPax <dirk.bruere(a)gmail.com> wrote: >John Larkin wrote: >> Testing some FTP stuff, threw up some test files... >> >> ftp://jjlarkin.lmi.net/Core_304bits.jpg >> >> ftp://jjlarkin.lmi.net/Core_4K.jpg >> >> ftp://jjlarkin.lmi.net/Core_4Kdetail.jpg > >I recall seeing the last one (or two) as examples. >Semis had just taken over. >I assume somebody who later owned a guide dog got to thread them... > The last one looks like the one I was just looking for. I took it out of a Linc 8 I believe.I still have the front panel. When I first started working, I was at DEC in 1969. I seem to recall seeing the women making memories. A real programmer could really toggle those front panel switches fast. greg
From: JosephKK on 11 Dec 2009 12:52 On Sat, 05 Dec 2009 19:18:45 +0000, ChrisQ <meru(a)devnull.com> wrote: >Jan Panteltje wrote: >> On a sunny day (Sat, 05 Dec 2009 10:51:36 -0800) it happened John Larkin >> <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in >> <kqalh59i8jsogn1t6p3ghuaop5c137qtoj(a)4ax.com>: >> >>> Testing some FTP stuff, threw up some test files... >>> >>> ftp://jjlarkin.lmi.net/Core_304bits.jpg >> >> 16 bits x 19?? >> >> >>> ftp://jjlarkin.lmi.net/Core_4K.jpg >> >> Amazing.. >> >> >>> ftp://jjlarkin.lmi.net/Core_4Kdetail.jpg >> >> Must have been expensive. >> >> >>> John >>> >>> >>> > >Don't recognise either of those as to manufacturer, but the last machine >that I had with core was an early pdp11/05, which eventually got shipped >back to the us. > >Ok, quiz time: how does core memory work ?. (and no cheating via google >etc :-)... > >Regards, > >Chris Even though i am nearly a week behind, i gotta step up to the plate. The most common form of core memory is called 3D. It is made up of bit planes (the third dimension). The cores have a very square B-H curve. In the bit planes there X and Y direction drive wires. Coincident current through the two wires produces enough field to make the addressed core switch direction of magnetization. The current pulse times are usually no longer than enough to ensure reliable operation. No other cores in the plane receive enough drive current induced flux to change state. Thus we need to add a sense wire to detect the core flux state changes. The sense wires are typically done diagonally to take advantage of the slightly larger aperture in that direction. Since the mechanism to readout the value of the core forces it to either the "0" or "1" state (a design property) any information to remain in the address must be rewritten. Thus another wire called inhibit which is wired in parallel with either the X or the Y drive lines and is driven with an opposing current flow which prevents changing the state of the core on the writeback half cycle. This allows three typical cycles read-writeback, read(erase)-write, and read-alter-write. These are the external interface definitions and read-alter-write may not be implemented. I hope that have not omitted too much.
From: JosephKK on 11 Dec 2009 13:02 On Sat, 5 Dec 2009 21:18:35 -0000, "Andrew Holme" <ah(a)nospam.co.uk> wrote: > >"ChrisQ" <meru(a)devnull.com> wrote in message >news:qmySm.123940$yM2.60574(a)newsfe10.ams2... >> Jan Panteltje wrote: >>> On a sunny day (Sat, 05 Dec 2009 10:51:36 -0800) it happened John Larkin >>> <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in >>> <kqalh59i8jsogn1t6p3ghuaop5c137qtoj(a)4ax.com>: >>> >>>> Testing some FTP stuff, threw up some test files... >>>> >>>> ftp://jjlarkin.lmi.net/Core_304bits.jpg >>> >>> 16 bits x 19?? >>> >>> >>>> ftp://jjlarkin.lmi.net/Core_4K.jpg >>> >>> Amazing.. >>> >>> >>>> ftp://jjlarkin.lmi.net/Core_4Kdetail.jpg >>> >>> Must have been expensive. >>> >>> >>>> John >>>> >>>> >>>> >> >> Don't recognise either of those as to manufacturer, but the last machine >> that I had with core was an early pdp11/05, which eventually got shipped >> back to the us. >> >> Ok, quiz time: how does core memory work ?. (and no cheating via google >> etc :-)... >> >> Regards, >> >> Chris > >The cores have hysteresis. You can't flip the direction of magnetisation >unless the current in the wires exceeds a certain threshold. You put half >the required current down an X wire and half down a Y wire. Only one core >at the X,Y intersection gets flipped. > >When you flip a core, you get a pulse induced in the read wire. This means >you have to do a destructive read. If you write a 1 and get a big pulse >back then you know it must have been a 0 before. If it was already a 1, you >only get a tiny pulse. Every read must be followed by a write to restore >the previous state. > >See my core memory page for 'scope captures of actual read pulses: > >http://www.holmea.demon.co.uk/Core/Flipper.htm > > Pretty good page. Would you like to discuss drive electronics? Nothing bigger than a TO-5 needed. 74hc138 decoders are fair game. Flat-pack packages ere fair game.
From: JosephKK on 11 Dec 2009 13:08
On Thu, 10 Dec 2009 02:00:12 -0800, Fred Abse <excretatauris(a)invalid.invalid> wrote: >On Sat, 05 Dec 2009 18:33:00 -0500, Spehro Pefhany wrote: > >> On Sat, 05 Dec 2009 14:05:33 -0800, the renowned John Larkin >> <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sat, 05 Dec 2009 13:33:53 -0800, Joerg <invalid(a)invalid.invalid> >>>wrote: >>> >>>>John Larkin wrote: >>>>> Testing some FTP stuff, threw up some test files... >>>>> >>>>> ftp://jjlarkin.lmi.net/Core_304bits.jpg >>>>> >>>>> ftp://jjlarkin.lmi.net/Core_4K.jpg >>>>> >>>>> ftp://jjlarkin.lmi.net/Core_4Kdetail.jpg >>>>> >>>> >>>>Here I must confess that I cruelly re-purposed some of those. People >>>>made matrix keyboards with them because the hysteresis provided an easy >>>>way to avoid contact bounce (you had to reset the cores before the next >>>>keystroke was accepted). So, snip, snip, snip, clicker, clicker, into a >>>>bag and gave them away. Back in the 70's keyboards with German layout >>>>were very expensive, some had odd interfaces, and buying 30-40 push >>>>button switches was a lot cheaper. You could buy them with a step and >>>>then glue a label onto the lower step. I think they still make them. >>> >>>There were some jukeboxes that used core memory - BIG cores, one per >>>record - to remember which records had been selected/paid for to play. >>> >>>John >> >> I vaguely remember a nuke simulator that used cores about 1" in >> diameter. >> > >Ampex made some very small core memories in the '70s. 32K in the size of >a paperback book. You needed a magnifier to see that the cores were >toroids. God knows how they threaded three wires through each one. Those were done by machine. > >I must have dumped dozens. Wish I'd kept one, now. The only thing I saved >was a few of the mumetal screening plates. Gotta love that mumetal. |