core memory
in [Design]
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From: John Larkin on 11 Dec 2009 21:09 On Sat, 12 Dec 2009 02:25:35 +0200, Paul Keinanen <keinanen(a)sci.fi> wrote: >On Fri, 11 Dec 2009 12:41:42 -0800, John Larkin ><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>Anybody remember 1K drams? I did a color graphic video generator, for >>oil/gas/product pipeline controls, using the strange 1K AMS parts. TI >>made a driver for them, too. They were differential read/write (5 volt >>write, millivolts read) and the memory cell was basically two >>capacitors and two connect fets. > >Are you referring to the 1103 ? No, I used an AMS part, 6002 I think. It had essentially two capacitors and two fets per cell, possibly structured as a 4-transistor dynamic latch with two access transistors. Either way, one wrote to it by applying a differential 5-volt level to a pair of pins, charging the addressed cell. Read connected to the same cell, and you got back a small differential signal. Actually, the chip didn't care whether you were reading or writing... it just connected you to the pair of caps. Read was destructive, like core, so after a read you had to recharge the caps then disconnect. It was noisy, like core. I've heard similarly bad stories about the 1103. Interesting: one of the founders of AMS was J. Larkin: http://www.computerhistory.org/semiconductor/companies.html John
From: JosephKK on 12 Dec 2009 00:11
On Sat, 12 Dec 2009 02:44:30 +0200, Paul Keinanen <keinanen(a)sci.fi> wrote: >On Fri, 11 Dec 2009 09:52:35 -0800, >"JosephKK"<quiettechblue(a)yahoo.com> wrote: > >> >>Since the mechanism to readout the value of the core forces it to >>either the "0" or "1" state (a design property) any information to >>remain in the address must be rewritten. Thus another wire called >>inhibit which is wired in parallel with either the X or the Y drive >>lines and is driven with an opposing current flow which prevents >>changing the state of the core on the writeback half cycle. >> >>This allows three typical cycles read-writeback, read(erase)-write, >>and read-alter-write. These are the external interface definitions >>and read-alter-write may not be implemented. > > >Perhaps this is just a naming convention, but isn't read-alter-write >the same as read-modify-write naming convention used by some other >manufacturers ? It is really just a difference in names. > >After all, in current DRAMs, when the RAS signal is asserted, the data >is read from all columns to a common area to be written back to the >memory cells in the same row. When the CAS drops, only the interesting >data is selected in the output multiplexer. > In the oldest versions. Then they changed things and you could get four successive address more quickly. This was called EDO DRAM about 20 years ago. Since then things have gone further in that direction. Gotta keep the caches fed so that they can feed the core. |