core memory
in [Design]
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From: John Larkin on 11 Dec 2009 15:41 On Fri, 11 Dec 2009 10:02:20 -0800, "JosephKK"<quiettechblue(a)yahoo.com> wrote: >On Sat, 5 Dec 2009 21:18:35 -0000, "Andrew Holme" <ah(a)nospam.co.uk> >wrote: > >> >>"ChrisQ" <meru(a)devnull.com> wrote in message >>news:qmySm.123940$yM2.60574(a)newsfe10.ams2... >>> Jan Panteltje wrote: >>>> On a sunny day (Sat, 05 Dec 2009 10:51:36 -0800) it happened John Larkin >>>> <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in >>>> <kqalh59i8jsogn1t6p3ghuaop5c137qtoj(a)4ax.com>: >>>> >>>>> Testing some FTP stuff, threw up some test files... >>>>> >>>>> ftp://jjlarkin.lmi.net/Core_304bits.jpg >>>> >>>> 16 bits x 19?? >>>> >>>> >>>>> ftp://jjlarkin.lmi.net/Core_4K.jpg >>>> >>>> Amazing.. >>>> >>>> >>>>> ftp://jjlarkin.lmi.net/Core_4Kdetail.jpg >>>> >>>> Must have been expensive. >>>> >>>> >>>>> John >>>>> >>>>> >>>>> >>> >>> Don't recognise either of those as to manufacturer, but the last machine >>> that I had with core was an early pdp11/05, which eventually got shipped >>> back to the us. >>> >>> Ok, quiz time: how does core memory work ?. (and no cheating via google >>> etc :-)... >>> >>> Regards, >>> >>> Chris >> >>The cores have hysteresis. You can't flip the direction of magnetisation >>unless the current in the wires exceeds a certain threshold. You put half >>the required current down an X wire and half down a Y wire. Only one core >>at the X,Y intersection gets flipped. >> >>When you flip a core, you get a pulse induced in the read wire. This means >>you have to do a destructive read. If you write a 1 and get a big pulse >>back then you know it must have been a 0 before. If it was already a 1, you >>only get a tiny pulse. Every read must be followed by a write to restore >>the previous state. >> >>See my core memory page for 'scope captures of actual read pulses: >> >>http://www.holmea.demon.co.uk/Core/Flipper.htm >> >> >Pretty good page. Would you like to discuss drive electronics? >Nothing bigger than a TO-5 needed. 74hc138 decoders are fair game. >Flat-pack packages ere fair game. TI made, for a while, integrated core stack drivers and sense amps. Ironic that as ICs got good enough to drive and sense cores, ICs got good enough to kill cores. Anybody remember 1K drams? I did a color graphic video generator, for oil/gas/product pipeline controls, using the strange 1K AMS parts. TI made a driver for them, too. They were differential read/write (5 volt write, millivolts read) and the memory cell was basically two capacitors and two connect fets. John
From: Rich Grise on 11 Dec 2009 18:02 On Fri, 11 Dec 2009 12:41:42 -0800, John Larkin wrote: > > TI made, for a while, integrated core stack drivers and sense amps. > Ironic that as ICs got good enough to drive and sense cores, ICs got > good enough to kill cores. > > Anybody remember 1K drams? I did a color graphic video generator, for > oil/gas/product pipeline controls, using the strange 1K AMS parts. TI > made a driver for them, too. They were differential read/write (5 volt > write, millivolts read) and the memory cell was basically two > capacitors and two connect fets. > I _almost_ used some DRAMs once, except by the time I got the Z80 board almost done, they were up to 64K. The Z80 had a "refresh" output, so using them would have been within the scope of my abilities at the time. ;-) Ufortunately, the project got interrupted and placed on the back burner, where it's been ever since. )-; Cheers! Rich
From: Jan Panteltje on 11 Dec 2009 18:40 On a sunny day (Fri, 11 Dec 2009 15:02:20 -0800) it happened Rich Grise <richgrise(a)example.net> wrote in <pan.2009.12.11.23.02.18.913050(a)example.net>: >On Fri, 11 Dec 2009 12:41:42 -0800, John Larkin wrote: >> >> TI made, for a while, integrated core stack drivers and sense amps. >> Ironic that as ICs got good enough to drive and sense cores, ICs got >> good enough to kill cores. >> >> Anybody remember 1K drams? I did a color graphic video generator, for >> oil/gas/product pipeline controls, using the strange 1K AMS parts. TI >> made a driver for them, too. They were differential read/write (5 volt >> write, millivolts read) and the memory cell was basically two >> capacitors and two connect fets. >> >I _almost_ used some DRAMs once, except by the time I got the Z80 board >almost done, they were up to 64K. The Z80 had a "refresh" output, so using >them would have been within the scope of my abilities at the time. ;-) > >Ufortunately, the project got interrupted and placed on the back burner, >where it's been ever since. )-; > >Cheers! >Rich I did a 265 kB RAMDISK with DRAM for the Z80. ftp://panteltje.com/pub/z80/ It was I/O mapped :-) The refresh was done by having it cycle through 512 address rows when not addressed. When addressed 512 bytes were read or written at any time, 'sector size'. It had write protest logic too, before writing a sector you had to do I/O to the unlock address. The procedure was: write to unlock address, write sector address low write sector address high write 512 bytes data. The idea was to read a complete single sided floppy (204800 Bytes = 40 tracks of 10 sectors of 512 bytes) into this RAMDISK, and then work from the RAMDISK. It was faster then anything at that time when doing that. Ran a C compiler on it, almost faster then the PC these days. 4 MHz clock.
From: Paul Keinanen on 11 Dec 2009 19:25 On Fri, 11 Dec 2009 12:41:42 -0800, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >Anybody remember 1K drams? I did a color graphic video generator, for >oil/gas/product pipeline controls, using the strange 1K AMS parts. TI >made a driver for them, too. They were differential read/write (5 volt >write, millivolts read) and the memory cell was basically two >capacitors and two connect fets. Are you referring to the 1103 ? Quite awful chip. The next generation 4 K dynamic or 1 K static were much easier to use.
From: Paul Keinanen on 11 Dec 2009 19:44
On Fri, 11 Dec 2009 09:52:35 -0800, "JosephKK"<quiettechblue(a)yahoo.com> wrote: > >Since the mechanism to readout the value of the core forces it to >either the "0" or "1" state (a design property) any information to >remain in the address must be rewritten. Thus another wire called >inhibit which is wired in parallel with either the X or the Y drive >lines and is driven with an opposing current flow which prevents >changing the state of the core on the writeback half cycle. > >This allows three typical cycles read-writeback, read(erase)-write, >and read-alter-write. These are the external interface definitions >and read-alter-write may not be implemented. Perhaps this is just a naming convention, but isn't read-alter-write the same as read-modify-write naming convention used by some other manufacturers ? After all, in current DRAMs, when the RAS signal is asserted, the data is read from all columns to a common area to be written back to the memory cells in the same row. When the CAS drops, only the interesting data is selected in the output multiplexer. |