Choice of Language for FPGA programming
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From: evilkidder on 2 Sep 2009 20:38 > > With a lot of money for some high-dollar tools, it is possible to > synthesize an FPGA design from a description written in the C > language. Then you place and route that synthesized netlist using the > FPGA vendor's tools (some available for free). > It's perhaps interesting to note that Altera's C2H compiler is available in their web-edition software; not a true C to hardware compiler, nor really free (OpenCore plus), but impressive none-the- less. I've been meaning to spend some time with it for a while now. Andy.
From: Mike Harrison on 3 Sep 2009 04:42 On Wed, 2 Sep 2009 15:25:01 -0700 (PDT), James Harris <james.harris.1(a)googlemail.com> wrote: >On 2 Sep, 15:34, Andy <jonesa...(a)comcast.net> wrote: > >... > >> But for starters, I would strongly recommend using an HDL like verilog >> or vhdl, and of those two, I recommend vhdl. Both are supported by the >> FPGA vendors' free design tools. > >Verilog is closer to C and may thus be a little easier for the OP to >learn. ...although as writing HDL is so different from programming, perhaps a _more_ different language would help reinforce the differences....
From: ganeshstha on 3 Sep 2009 07:22 >On Wed, 2 Sep 2009 15:25:01 -0700 (PDT), James Harris <james.harris.1(a)googlemail.com> wrote: > >>On 2 Sep, 15:34, Andy <jonesa...(a)comcast.net> wrote: >> >>... >> >>> But for starters, I would strongly recommend using an HDL like verilog >>> or vhdl, and of those two, I recommend vhdl. Both are supported by the >>> FPGA vendors' free design tools. >> >>Verilog is closer to C and may thus be a little easier for the OP to >>learn. > >..although as writing HDL is so different from programming, perhaps a _more_ different language >would help reinforce the differences.... > > Thank you all for the suggestions. --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
From: johnp on 3 Sep 2009 10:10 On Sep 3, 4:22 am, "ganeshstha" <ganesh_s...(a)hotmail.com> wrote: > >On Wed, 2 Sep 2009 15:25:01 -0700 (PDT), James Harris > <james.harri...(a)googlemail.com> wrote: > > >>On 2 Sep, 15:34, Andy <jonesa...(a)comcast.net> wrote: > > >>... > > >>> But for starters, I would strongly recommend using an HDL like > verilog > >>> or vhdl, and of those two, I recommend vhdl. Both are supported by > the > >>> FPGA vendors' free design tools. > > >>Verilog is closer to C and may thus be a little easier for the OP to > >>learn. > > >..although as writing HDL is so different from programming, perhaps a > > _more_ different language > > >would help reinforce the differences.... > > Thank you all for the suggestions. > > --------------------------------------- > This message was sent using the comp.arch.fpga web interface onhttp://www..FPGARelated.com My personal opinion is for Verilog. It's a much tighter language. Maybe it's just bad luck, but I've seen lots of bad design and coding in VHDL, Verilog designs I've seen seem to be better quality. Maybe that's just a coincidence. BUT... the real issue is that designing for an FPGA is different from programming. The parallelism, timing issues, clock crossing, input/output timing, etc are flat out different concepts that most programmers don't appreciate. It's not the language that's the hurdle, it's all the h/w design practices that lead to problems. John Providenza
From: Andy on 3 Sep 2009 14:55
On Sep 2, 5:25 pm, James Harris <james.harri...(a)googlemail.com> wrote: > On 2 Sep, 15:34, Andy <jonesa...(a)comcast.net> wrote: > > ... > > > But for starters, I would strongly recommend using an HDL like verilog > > or vhdl, and of those two, I recommend vhdl. Both are supported by the > > FPGA vendors' free design tools. > > Verilog is closer to C and may thus be a little easier for the OP to > learn. > > It's probably been covered many times but as a beginner myself it > would be interesting to know why you recommend VHDL. Care to > elucidate? > > James (Other than my personal bias) : Given the differences between coding for SW and coding for HW, VHDL is better at keeping a new user from making some ignorant mistakes. A new designer with a SW background is more likely to make typical "SW" mistakes in a language that looks more like the SW he is used to. Sometimes keeping the syntax apart helps in this regard. On the other hand, if one's SW background is in ada, you could make exactly the same argument in favor of verilog ;^) That said, VHDL lets you use non-shared variables (blocking assignments) to get "SW-style" update semantics, without the potential for race conditions that verilog has, to create HW that will behave just like the code simulates (on a clock-cycle basis). With effort and skill obtained through experience, this can be accomplished in verilog too, but we're not talking about an experienced HW designer. If one's background in SW is more advanced (e.g. a seasoned SW engineer), then the applicable principles of good SW design (appropriate abstraction, information hiding, testing, etc.) are more easily applied in VHDL than in verilog. Andy |