Choice of Language for FPGA programming
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From: Nico Coesel on 6 Sep 2009 17:37 Mike Treseler <mtreseler(a)gmail.com> wrote: >Jon wrote: >> Sure, VHDL is better for a new user. Writing the same thing again and >> again and again and again helps you remember it. > >I will admit that most vhdl users do not >use functions and procedures for this, >but it is possible -- both for synthesis >and simulation code. Just for fun: google for code for a priority encoder. 9 out of 10 write it as seperate equations for each condition. If you create a procedure, its only 3 lines of code! -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... "If it doesn't fit, use a bigger hammer!" --------------------------------------------------------------
From: Mark McDougall on 6 Sep 2009 20:54 Nico Coesel wrote: > Like C# is replacing C/C++. ROTFL!!! You're taking the p*ss, right??? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
From: Phil Jessop on 7 Sep 2009 04:21 "Nico Coesel" <nico(a)puntnl.niks> wrote in message news:4aa42b18.1299851468(a)news.planet.nl... > Mike Treseler <mtreseler(a)gmail.com> wrote: > >>Jon wrote: >>> Sure, VHDL is better for a new user. Writing the same thing again and >>> again and again and again helps you remember it. >> >>I will admit that most vhdl users do not >>use functions and procedures for this, >>but it is possible -- both for synthesis >>and simulation code. > > Just for fun: google for code for a priority encoder. 9 out of 10 > write it as seperate equations for each condition. If you create a > procedure, its only 3 lines of code! > I just double click, insert 74148. Job done. 0 lines of code.
From: Jonathan Bromley on 7 Sep 2009 04:18 On Fri, 04 Sep 2009 17:35:28 GMT, Nico Coesel wrote: >I still see no difference between the development flow for a cpu and >an FPGA. Its all about idea -> specification -> implementation -> >verification / testing. That's true so far. Indeed, it's unfortunate that so few HDL folk buy in to the good ideas about that flow that have been developed (at cost of great pain) by the software community over the past few decades. >The only real difference is that a CPU executes a program >sequentially and an FPGA executes its program in parallel. Neither of those things is necessarily true these days. Parallelism is endemic in compute platforms today (although most programmers are still in denial about it) and it's easy enough to get an FPGA to have sequential behavior of various kinds. But it is clearly true that FPGA users must be prepared to work with very fine-grained parallelism, which is precisely why they have programming languages (VHDL, Verilog) that explicitly support it. Conventional imperative languages have no explicit support for fine- grained parallelism; therefore, it falls to the tools to infer parallelism from the sequential code. Sometimes tools can do that very well; most times they need heavy hints; occasionally they completely fail. It's not surprising that many of us are reluctant to support a wholesale move to procedural languages for hardware design. As I've said before many times, I completely fail to understand why there has been so little take-up in the software community of languages that explicitly support parallel execution (occam, Ada...). The usual argument is that it's easier to reason about sequential than about concurrent programs. That argument is, in my opinion, baseless; in the languages I've mentioned, concurrency is well-managed and easy to reason about. Ho hum. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley(a)MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
From: HT-Lab on 7 Sep 2009 05:14
"Mark McDougall" <markm(a)vl.com.au> wrote in message news:4aa459df$0$27631$5a62ac22(a)per-qv1-newsreader-01.iinet.net.au... > Nico Coesel wrote: > >> Like C# is replacing C/C++. > > ROTFL!!! You're taking the p*ss, right??? He is. Have a look at this article, http://www.embedded.com/design/218600142 I am glad to be a man :-) Hans www.ht-lab.com > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 |