Choice of Language for FPGA programming
in [FPGA]
|
Prev: OpenSPARC T1 or T2 on Altera EP2S60 or EP2S90
Next: Where to find source code for Xilinx ML507 board demos?
From: Jonathan Bromley on 4 Sep 2009 03:56 On Fri, 04 Sep 2009 10:24:26 +1000, Mark McDougall wrote: >VHDL for synthesizable modules with a Verilog >testbench for simulation. Couldn't agree more. Even after the SystemVerilog enhancements, VHDL is a demonstrably superior language for RTL design - I can go into *much* more detail if you want, but I strongly suspect you don't want :-) But Verilog, and especially SystemVerilog, makes testbenches very, very much easier than VHDL. >it's definitely an advantage to be conversant in both Again, I agree strongly. However, many folks don't have the luxury of tools that support mixed-language simulation, and most folks don't have the luxury of tools that support SystemVerilog simulation. Back to the real world :-( -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley(a)MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
From: Jan Decaluwe on 4 Sep 2009 05:29 ganeshstha wrote: > Hi, > I am new to the FPGA world. I am using chipcon CC2400 board and has the > Xilinx's XC2S200E FPGA. Is it possible to program it program the FPGA in > C? > I donot have any experience in VHDL and verilog. http://www.myhdl.org/doku.php/why -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.com
From: Poojan Wagh on 4 Sep 2009 06:54 On Sep 4, 2:56 am, Jonathan Bromley <jonathan.brom...(a)MYCOMPANY.com> wrote: > On Fri, 04 Sep 2009 10:24:26 +1000, Mark McDougall wrote: > >VHDL for synthesizable modules with a Verilog > >testbench for simulation. > > Couldn't agree more. Even after the SystemVerilog > enhancements, VHDL is a demonstrably superior language > for RTL design - I can go into *much* more detail > if you want, but I strongly suspect you don't want :-) > > But Verilog, and especially SystemVerilog, makes > testbenches very, very much easier than VHDL. Hi, Jonathan. Actually, I would benefit from an elucidation on why VHDL is superior to SystemVerilog for RTL design. I shifted into Verilog, because I came from an analog background and I was familiar with Verilog-A. I've recently hired a seasoned VHDL designer, and we're trying to determine which language to code in as a general rule (leaving room for warranted exceptions, of course). Based on this: http://www.systemverilog.org/techpapers/date04_systemverilog..pdf I was under the impression that SystemVerilog is now up to speed with VHDL on all the usage scenarios that Verilog lacked. I realize a lot of these decisions come from personal experience and preference. However, I want to be open to all points of view given that I can't predict what my future experience will be.
From: johnp on 4 Sep 2009 10:45 On Sep 4, 3:54 am, Poojan Wagh <poojanw...(a)gmail.com> wrote: > On Sep 4, 2:56 am, Jonathan Bromley <jonathan.brom...(a)MYCOMPANY.com> > wrote: > > > On Fri, 04 Sep 2009 10:24:26 +1000, Mark McDougall wrote: > > >VHDL for synthesizable modules with a Verilog > > >testbench for simulation. > > > Couldn't agree more. Even after the SystemVerilog > > enhancements, VHDL is a demonstrably superior language > > for RTL design - I can go into *much* more detail > > if you want, but I strongly suspect you don't want :-) > > > But Verilog, and especially SystemVerilog, makes > > testbenches very, very much easier than VHDL. > > Hi, Jonathan. > > Actually, I would benefit from an elucidation on why VHDL is superior > to SystemVerilog for RTL design. I shifted into Verilog, because I > came from an analog background and I was familiar with Verilog-A. I've > recently hired a seasoned VHDL designer, and we're trying to determine > which language to code in as a general rule (leaving room for > warranted exceptions, of course). > > Based on this:http://www.systemverilog.org/techpapers/date04_systemverilog.pdf > I was under the impression that SystemVerilog is now up to speed with > VHDL on all the usage scenarios that Verilog lacked. I realize a lot > of these decisions come from personal experience and preference. > However, I want to be open to all points of view given that I can't > predict what my future experience will be. I think we can agree on one thing - Verilog and VHDL are like toothpaste. You'll have a favorite, but you'll tolerate the other if you have to. The real problem I see is that no matter what the language, at some point you have to deal with clock domain crossing, meta-stability, setup/hold issues, logic depth, etc. Neither language can eliminate these traps. A newbie who comes into h/ w design from a s/w background probably doesn't appreciate how tricky these problems can be. They focus on the language to use and not what the subtle design problems are. John Providenza
From: Nico Coesel on 4 Sep 2009 13:31
James Harris <james.harris.1(a)googlemail.com> wrote: >On 2 Sep, 15:34, Andy <jonesa...(a)comcast.net> wrote: > >... > >> But for starters, I would strongly recommend using an HDL like verilog >> or vhdl, and of those two, I recommend vhdl. Both are supported by the >> FPGA vendors' free design tools. > >Verilog is closer to C and may thus be a little easier for the OP to >learn. I strongly disagree. Verilog always looks like a netlist to me. No beginning - no end. VHDL is much more structured. Agreed Verilog can leeds to results faster, but VHDL is definitely more powerful. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... "If it doesn't fit, use a bigger hammer!" -------------------------------------------------------------- |