Choice of Language for FPGA programming
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From: Petter Gustad on 3 Sep 2009 15:43 Andy <jonesandy(a)comcast.net> writes: > for SW and coding for HW, VHDL is better at keeping a new user from > making some ignorant mistakes. A new designer with a SW background is So you would never recommend VHDL to an Ada programmer would you? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
From: glen herrmannsfeldt on 3 Sep 2009 16:14 Andy <jonesandy(a)comcast.net> wrote: (snip on verilog and VHDL) < (Other than my personal bias) : Given the differences between coding < for SW and coding for HW, VHDL is better at keeping a new user from < making some ignorant mistakes. A new designer with a SW background is < more likely to make typical "SW" mistakes in a language that looks < more like the SW he is used to. Sometimes keeping the syntax apart < helps in this regard. On the other hand, if one's SW background is in < ada, you could make exactly the same argument in favor of verilog ;^) I don't agree, but I believe it could be personal preference. For one, I did some logic design with TTL gates before learning verilog, so I know how to think in terms of logic. Verilog isn't really that much like C. There are people using C as an HDL, and I completely agree that is a bad idea. < That said, VHDL lets you use non-shared variables (blocking < assignments) to get "SW-style" update semantics, without the potential < for race conditions that verilog has, to create HW that will behave < just like the code simulates (on a clock-cycle basis). With effort and < skill obtained through experience, this can be accomplished in verilog < too, but we're not talking about an experienced HW designer. Oh, also, my verilog uses very little behavioral mode, one big exception being flip-flops. Also case blocks for state machines. < If one's background in SW is more advanced (e.g. a seasoned SW < engineer), then the applicable principles of good SW design < (appropriate abstraction, information hiding, testing, etc.) are more < easily applied in VHDL than in verilog. Maybe. But then again, C wasn't my first language. I can think in a variety of software languages, ADA not being one. -- glen
From: Andy on 3 Sep 2009 17:52 On Sep 3, 2:43 pm, Petter Gustad <newsmailco...(a)gustad.com> wrote: > > So you would never recommend VHDL to an Ada programmer would you? I would still recommend VHDL, but I couldn't very well use that argument. Andy
From: Mark McDougall on 3 Sep 2009 20:24 Mike Harrison wrote: > ..although as writing HDL is so different from programming, perhaps a > _more_ different language would help reinforce the differences.... Actually, that's a _very_ good point. And to weigh in with my $0.02 worth on the Verilog vs VHDL debate... My "preference" is VHDL, but I suspect that has a lot to do with the fact that the requirements for our first major FPGA project stipulated that the design be coded in VHDL as far as possible. So I find most of my synthesizable code is done in VDHL to this day. Interestingly, said project included some 3rd party cores, one of which was written in Verilog with a very large and complex testbench. We ended up expanding on that testbench to encompass the whole design. And so I found my preference for writing testbench code was in Verilog, rather than VHDL. And I would maintain that IMHO it's _definitely_ quicker and easier to write testbenches in Verilog. Subsequently, I found myself continuing this pattern on later projects - VHDL for synthesizable modules with a Verilog testbench for simulation. However, more recently I've forced myself to write testbench code in VHDL as well - mainly to simplify development requirements and ease the burden on my poor brain cells. But it's definitely an advantage to be conversant in both - and I do still find it necessary to modify the odd Verilog core. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
From: HT-Lab on 4 Sep 2009 03:19
"glen herrmannsfeldt" <gah(a)ugcs.caltech.edu> wrote in message news:h7p82b$mgn$1(a)naig.caltech.edu... > Andy <jonesandy(a)comcast.net> wrote: > (snip on verilog and VHDL) > > < (Other than my personal bias) : Given the differences between coding > < for SW and coding for HW, VHDL is better at keeping a new user from > < making some ignorant mistakes. A new designer with a SW background is > < more likely to make typical "SW" mistakes in a language that looks > < more like the SW he is used to. Sometimes keeping the syntax apart > < helps in this regard. On the other hand, if one's SW background is in > < ada, you could make exactly the same argument in favor of verilog ;^) > > I don't agree, but I believe it could be personal preference. > For one, I did some logic design with TTL gates before learning > verilog, so I know how to think in terms of logic. > > Verilog isn't really that much like C. There are people using > C as an HDL, and I completely agree that is a bad idea. Don't be too quick to dismiss C for HDL, there are lots of companies that develop algorithms in Matlab/C/C++/SC and then pass it on to a poor engineer to "quickly" translate into VHDL/Verilog. Then a month later they require the same algorithm but 5 times faster or with a "subtle change" which normally results (requires) a costly redesign. For those applications you really want to use an untimed language like C/C++ and use a tool (CatapultC/BlueSpec/ Forte/Synfora/etc...) to do all the design exploration (resource mapping/adding pipelines/concurrency/etc) for you. Given the progress these tools are making (most can now also handle control path as well) and the amount of money companies like Intel/AMD are pouring into sequential to concurrent research I wouldn't be surprise if the future of RTL is neither VHDL nor Verilog..... Hans www.ht-lab.com |