FPGA

Problems with NIOS II PIO interrupt
Hi, I've some trouble with NIOS II PIO interrupts and need some help. The pio port is configured as follows: Width= 2 bits Both input and output ports (not tri-state) Synchronously capture: Rising Edge IRQ= edge sensitiv I dont want to use HAL to keep the code size small, that's why I use alt_main. static ... 15 Sep 2006 13:10

TI TFP410 DVI transmitter help?
I am trying to use I2C to configure TI TFP410 DVI transmitter. I put differential clock input and VSYNC/HSYNC with the data. I suppose to get 1600x1200 image on the monitor. Basically, I just want to show a simple image and my hardware pins configuration is like below: DKEN (35) <--- GND /PD (10) <--- GND ... 8 Sep 2006 05:35

RLOC problems
I'm playing around a bit with RLOC and I'm getting some weird results. My top level file has these instantiations in it: (* RLOC = "X0Y0" *) rloc_reg32 sourcefds(.clk_i(clk_i),.D(internal2),.Q(thebus)); (* RLOC = "X60Y0" *) rloc_reg32 destfds(.clk_i(clk_i),.D(thebus),.Q(internal4)); And rloc_reg32 lo... 6 Sep 2006 08:19

Packages for ORCAD
Hello. Do anybody have ORCAD library for Xilinx xc3s1500 in FG320 package and TI TMS320C6713BGDP300? Thanks, Dmitry. ... 6 Sep 2006 12:04

Open-source CableServer for Impact on sourceforge.net
Hi All, Here is a open-source CableServer replacement,ent for Impact. Currently Parallel III and Alter ByteBlaster are supported, but any 3rd party can be implemented easily and can be used from Impact. I've tested only Impact 8.2, if anybody has any problem with 7.1, please let me know! Impact and Xilinx C... 8 Sep 2006 08:20

FSL read/write problems
Hi all, I'm trying to implement a correlator as a coprocessor on the FSL bus. The first thing I've done is generate the FSL example using the create peripheral wizard in EDK 8.1 and hooked it up to the MicroBlaze. When I do a blocking write or read the MB stalls - my understanding is that this will happen if th... 30 Aug 2006 00:35

FPGA -> SATA?
I am looking for a way to read/write to a SATA drive from an FPGA. I've looked around. Nothing seems to fit the bill. Any ideas worth considering? Thanks, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin To send private email: email = x(a)y.com where: x = "martineu" y = "pacbell.net" ... 30 Aug 2006 04:47

Open source Xilinx JTAG Programmer released on sourceforge.net
Hi All, I've released the first version of my Xilinx JTAG programmer for Win32/Linux. Supports Parallel III Cable and Digilent USB. Check and of message for supported devices! http://sourceforge.net/projects/xilprg This is a very first version, so please be patient with me and provide as much info as pos... 25 Aug 2006 21:55

uclinux on spartan-3e starter kit
"David" <aresolimpico(a)gmail.com> schrieb im Newsbeitrag news:1156353617.495934.108430(a)b28g2000cwb.googlegroups.com... i get this errors using the rev02 i get 2 errors and one warning how i can resolve it? WARNING:MDT - The installed version of EDK tools is 8.1, while project was created with versi... 18 Sep 2006 04:07

CPU design
Jim Granville wrote: Frank Buss wrote: <snip> The only problem is that you need a C compiler or something like this, because writing assembler with this reduced instruction set looks like it will be no fun. just got quartus II after 1/2 hr seems ok, after setting top level!! i wonder i... 1 Sep 2006 04:15