FPGA

EDK 8.2 Block RAM error
hi, it seems that either EDK 8.2 or ISE 8.2 has still some issues with the BRAM inits, if an EDK system has more than 1 BRAM block, then the BMM file is generated "looking good", makes sense but when it passes NGCbuild then only the first memory block gets the "PLACED" locations assigned, the second one stays af... 30 Nov 2006 15:52

ise 7.1
i'm trying to install ise 7.1 on solaris 10 running on parallels VM. Setup quits after the following meesages: /tmp/windu/windu_clientd50: cannot execute nohup: ./windu_registryd50: no such file or directory Has anyone ever seen this or have a clue how i might get around it? ... 16 Nov 2006 02:18

FFT in VHDL (or Verilog) Tutorial
Hello, Can someone point me to simple implementation of FFT in VHDL(or Verilog) with testbench and good step-by-step description. I have implementation from Xilinx (which I will eventually use for hardware implementation), but I find it rather confusing (lack of vhdl experience). Algorithm used, # of points, Rad... 21 Nov 2006 13:47

xupv2p
Helllo, Does anyone know about transfering data between two xupv2p boards, that is from one board to another? I appreciate your help nmichou ... 15 Nov 2006 15:09

C3188A - 1/3"Digital Output Colour Camera Module
Hello, Is there anyone who interface the C3188A - 1/3" Digital Output Colour Camera Module with an fpga. I am waiting for your answers. Thanks ... 10 Nov 2006 15:33

Cypress 68013 - Xilinx FPGA
Hi everyone, I am trying to add a USB 480Mbps interface to my fpga design which will stream data in one direction only from the FPGA to PC. The avnet evaluation board I have has the Cypress 68013 chip. Can anybody point me in the right direction of where to start (or which is the most suitable application no... 24 Nov 2006 04:39

JTAG connection for chipscope
Hi, I need help for solving the following problem.I am trying to connect to ML461 JTAG port from PC parallel port by using XILINX parallel cable through chipscope.But it couldn't connect properly.It gives the following error. ERROR: Socket Open Failed. localhost/127.0.0.1:50001 localhost java.net.ConnectE... 18 Nov 2006 02:49

xilkernel cache
hi i have a micorblaze projet on a spartan 3 wit 8 k instruction an data cache linked with the ddr ram. the memory test and the peripheral test works fine. now i started to write my own applicatin using xilkernel and lwip. my problem now is the my application does not work. it compiles fine but whe i try to dow... 30 Oct 2006 12:06

Dual Port RAM
Hi I am trying to infer a Xilinx dual port block ram with different address and data widths. I want to infer it in my code and then get Synplify to recognise it. I can do this if the address and data are the same but dont know how if they are different. Thanks J ... 2 Nov 2006 06:53

Have you experience to program the APA series using FlashPro Lite?
I have flashpro-lite programmer of actel. But, in use, very uncomportable because i don't know how to solve the error..... Any one have the error books? This is the errors i faced... programmer 'FPL31LPT1' : Scan Chain... Error: programmer 'FPL31LPT1' : Signal Integrity Failure Integrity Check Pattern No... 18 Nov 2006 03:20