FPGA

Xilinx Spartan6: ISERDES2 and BUFIO2 (xc6slx45-2csg324)
Hello, I have been trying to fit a deserializer into a Spartan 6 but I am running into some problems: - I am able to fit my design if the deserializer is on a top or a bottom bank. I can't get it fit when the deserializer is on the left or the right bank. There seems to be a problem with the BUFIO2. This is t... 17 Sep 2009 07:52

SOLVED: Problems with simulation of amforth in VMLAB...
A few months ago I've reported problems related to simulation of amforth ( http://amforth.sf.net ) in the VMLAB ( http://www.amctools.com/vmlab.htm) details are described here: http://www.amctools.com/cgi-bin/yabb2/YaBB.pl?num=1240766206 I have discovered that the problems are caused by the fact, that VMLAB does n... 14 Sep 2009 15:16

Spartan-6 - Pre-release Information on Drigmorn3.
Outline information on our first Spartan-6 release Drigmorn3 is now available. Drigmorn3 is aimed as a starter kit type product but also good for MicroBlaze and other processor applications. Details of this product http://www.enterpoint.co.uk/component_replacements/drigmorn3.html. We may be upgrading this product... 13 Sep 2009 11:43

Xilinx TCL and Cygwin
I was just starting to try to do some playing with TCL, and ran into an interesting problem. If you're running bash through Cygwin: A) Trying to run xtclsh just hangs entirely, forcing you to kill the process. B) The built-in Cygwin tclsh seems to work fine, but when you try to execute the line >> source $env... 9 Sep 2009 18:44

Xilinx USB CABLE SCHEMATIC NOW OFFICIALLY PUBLISED !!!! ::) yippii ?yee
On Aug 1, 1:06 am, "Antti.Luk...(a)googlemail.com" <Antti.Luk...(a)googlemail.com> wrote: On Jul 31, 3:48 pm, "markman" <mark...(a)163.com> wrote: On Jun 28, 12:59=A0pm, "maxascent" <maxasc...(a)yahoo.co.uk> wrote: What about the software required for theUSBchip and CPLD? Is this included wit... 9 Sep 2009 03:04

Traversing hierarchy in UCF works for OBUF, but not IOBUF, please help
Hi all, I have an SDRAM interface buried deep inside the hierarchy. I was able to instantiate OBUF for the control & address signals and traverse the hierarchy from the UCF file to tie the signals to the FPGA pins. However, when I try to do something similar for the IOBUFs, I get an error of the type ... 10 Sep 2009 02:31

IMPACT-Xilinx Platform Cable USB II
I have a custom board that uses usb and has 2 fpgas (spartan3 200 - spartan 3 4000) I am using Xilinx platform cable USB II to program the fpga I am using windows xp pro I am using Xilinx 9.1.03i When I press initialize chain button in impact tool some popup question says=> "There are many unknown devices bei... 8 Sep 2009 19:17

Bidirectional Bus
After programming an FPGA, XC3S250EVQ100, via Slave Parallel through an FTDI USB translator and a CPLD, XC2C64AVQ100, which synchronize data and fpga_cclk into the FPGA the done pin goes high. The problem I am having is the bidirectional does not release and allow the FPGA to drive the data bus to CPLD and then fin... 7 Sep 2009 22:17

Spartan 3 loading from MCU slave serial problems
Hello, I've run into a problem bit bang loading (Slave serial) the Spartan 3 from an MCU. The Spartan 3 is setup with M0,M1 & M2 tied high (verified). I can verify the active CCLK and DIN during programming, and I can see transitional changes to INIT_L and DONE during programming. I follow the instructions ... 8 Sep 2009 11:23

Where to find source code for Xilinx ML507 board demos?
>Hello FPGA Gurus! I have just bought Xilinx ML507 board in order to learn Xilinx FPGAs and ISE tools. Latest experience with XC3130 FPGAs was 13 years ago, but those chips and tools were very easy to use. I was able to run all demos, I have downloaded all possible docs and refernce designs from Xilinx sit... 3 Sep 2009 18:26