FPGA

Spartan-3E starter kit
Any body knows when the Spartan-3E starter kit will be availaible from Xilinx? Website says 4th quarter. Isn't it 4th quarter already? ... 9 Nov 2005 21:41

Error (XST): translate terminal to FCT
Dear During synthesizing in XST of ISE 6.3, following error (?) is encountered.... Does anyone have experience on this trouble? Thankyou for information in advance ---------------- failed to translate terminal to FCT $n0133[7] = If $n0243 Then $n0297[7] If $n0245 Then $n0299[7] If $n0247 Then $n03... 16 Oct 2005 18:54

3.3v<->5V
Hi all, I am new to logic design in general, but I am getting an FPGA development board (the Spartan-3 board from xilinx) and I hope to make a small circuit for connecting to an old microcomputer and some SRAM. For this project, I will need a bunch of (~60) 5V I/O lines, but the FPGA's lines are all 3.3V logic. ... 16 Oct 2005 07:26

Small C Compiler for Picoblaze
Dear all, last year I started to design the back end of a "Small C" compiler for the picoblaze microcontroller. (You can download it on www.poderico.co.uk) I haven't done much for the last two months... but now I'm ready to continue my development. I'm looking for some help in the development. Do you want to help... 29 Sep 2005 09:33

Xilinx Spartan-3
Hello! I have an application with a Spartan-3 mainboard and 3 spartan-3-based daughterboards -- we had planned on connecting the daughterboards to the mainboard via SATA connectors, and running a 300 Mbps LVDS link in each direction (M->D and D->M). We had hoped that the daughterboards could do clock-recovery of th... 26 Sep 2005 09:24

modelsim simulation problem
I am trying to load a EDK design in modelsim for simulation.I can successfully compile the files but when I try to simulate the project, I get the following error. # Loading /home/simulation_library/simtemp/unisim.ppc405(ppc405_v) # ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1n... 12 Sep 2005 16:44

CPLD Jitter
The dividers and the phase detector of my experimental frequency synthesizer are implemented in a 15ns Altera MAX7000S CPLD. I've tried different multiplication factors (kN) to see how the close-in phase noise varies. At a 1 KHz offset, I get: -82 dBc/Hz for N=198 (VCO=19.8 MHz, comparison freq = 100 KHz) -95 ... 30 Aug 2005 16:44

Evolutionary VHDL code example
Hello everyone Does anyone where I can find a simple VHDl code example based on evolutionary algorithms.I am doing a project on evolvable hardware. This will help me get a start on the implementation of Evolvable Hardware. Ankit Parikh Manukau Institute Of Technology ... 20 Aug 2005 18:19

NIOS II + USB 2.0 host
Hi, We will soon be using the Nios II as embedded controller and we would like to add a High Speed (HS) USB 2.0 hosting feature that is capable or providing a sustained transfer rate of 20 MBytes/sec. to an external HS USB 2.0 device. I realize that there are a limited number of HS USB 2.0 hosts devices/IP co... 17 Jul 2005 22:07

ISE7.1 PAR Warinng: excessive skew because 1 NON-CLK pins...
I am getting the following warning on a Virtex-II design: WARNING:Route - CLK Net:clk50_BUFGP may have excessive skew because 1 NON-CLK pins failed to route using a CLK template. My question is how can I find the problematic pin? A similar question was asked here in the past, but the discussion slipped into ... 13 Jun 2005 21:38