Freq. Independent Phase Shifter
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From: Frank Buss on 14 May 2010 01:12 John Larkin wrote: > http://www.highlandtechnology.com/DSS/T346DS.html > > This uses an FPGA clocked at 128 MHz, a 32-bit phase accumulator, a > 4096 point sine lookup table, and a 14 bit DAC per channel. It makes > sines from 0 to 32 MHz with 0.015 Hz frequency resolution. It's a > textbook DDS design, but with phase-rotation adders in the lookup > table address paths and multipliers for amplitude. There are also > adders into the accumulator inputs to allow FM and chirps and such. Nice. For sine wave, DDS is a good idea. But when you generate a square wave with your device with e.g. 31.7 MHz, what is your maximum cycle-to-cycle jitter? BTW: Where can I buy your devices and do you have a price list on your webpage? -- Frank Buss, fb(a)frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
From: Winston on 14 May 2010 02:20 On 5/13/2010 9:24 PM, John Larkin wrote: > On Thu, 13 May 2010 20:52:25 -0700, Winston<Winston(a)bigbrother.net> > wrote: > >> On 5/13/2010 6:57 PM, John Larkin wrote: >> >> (...) >> >>> Not exactly. If you address the sine lookup table with a >>> fixed-frequency-clocked phase accumulator, instead of a counter, you >>> can tune the sine frequency to as fine a resolution as you want, just >>> by using more bits in the accumulator. >> >> (...) >> >> So the Phase Accumulator itself is a state machine which creates >> a binary version of the next point to be output predicated on >> the previous point and the frequency control word. >> >> It is starting to soak in. Thanks! >> >> --Winston >> > > I guess. > > Imagine a 32-bit clockable binary register, just 32 D-type flipflops. > Call the value in the register R. Every clock, add a 32-bit value F to > it. so > > At every clock > > R = R + F > > F is our 32-bit frequency set register. > > If R=1, it will take 2^32 clocks for R to make a full cycle back to > where it started. If R=2, it will cycle around in 2^31 clocks. > > Take the 12 most significant bits of the R register and use them to > address a sinewave lookup table, and use the result to load a DAC at > the same clock rate. > > What's cool is that you can put all sorts of values into F, and the > frequency of the DAC is proportional to the value F. For small values > of F, it will take many clocks before you bump the upper 12 bits and > advance one location in the lookup table. As F gets bigger, you'll > start hopping around the table in bigger jumps, skipping some entries. > But if you lowpass filter the DAC output, you always get a sine wave. > The frequency-set resolution is Fclk/2^32, which is pretty fine. If > you use a 64-bit register, resolution is Fclk/2^64. > > It's really very simple, an easy to build in an FPGA. *Much clearer!* Thanks for the explanation. --Winston
From: Tim Williams on 14 May 2010 05:01 That's all well and good, but I could do it in fewer transistors. ;-) (Ya ya, neglecting the asymptotically zero cost of transistors.) Tim -- Deep Friar: a very philosophical monk. Website: http://webpages.charter.net/dawill/tmoranwms "John Larkin" <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote in message news:25jpu5dmgplv21je7rd5a29hak23j2shsk(a)4ax.com... > On Thu, 13 May 2010 20:52:25 -0700, Winston <Winston(a)bigbrother.net> > wrote: > >>On 5/13/2010 6:57 PM, John Larkin wrote: >> >>(...) >> >>> Not exactly. If you address the sine lookup table with a >>> fixed-frequency-clocked phase accumulator, instead of a counter, you >>> can tune the sine frequency to as fine a resolution as you want, just >>> by using more bits in the accumulator. >> >>(...) >> >>So the Phase Accumulator itself is a state machine which creates >>a binary version of the next point to be output predicated on >>the previous point and the frequency control word. >> >>It is starting to soak in. Thanks! >> >>--Winston >> > > I guess. > > Imagine a 32-bit clockable binary register, just 32 D-type flipflops. > Call the value in the register R. Every clock, add a 32-bit value F to > it. so > > At every clock > > R = R + F > > F is our 32-bit frequency set register. > > If R=1, it will take 2^32 clocks for R to make a full cycle back to > where it started. If R=2, it will cycle around in 2^31 clocks. > > Take the 12 most significant bits of the R register and use them to > address a sinewave lookup table, and use the result to load a DAC at > the same clock rate. > > What's cool is that you can put all sorts of values into F, and the > frequency of the DAC is proportional to the value F. For small values > of F, it will take many clocks before you bump the upper 12 bits and > advance one location in the lookup table. As F gets bigger, you'll > start hopping around the table in bigger jumps, skipping some entries. > But if you lowpass filter the DAC output, you always get a sine wave. > The frequency-set resolution is Fclk/2^32, which is pretty fine. If > you use a 64-bit register, resolution is Fclk/2^64. > > It's really very simple, an easy to build in an FPGA. > > John > > >
From: John Larkin on 14 May 2010 10:03 On Fri, 14 May 2010 07:12:06 +0200, Frank Buss <fb(a)frank-buss.de> wrote: >John Larkin wrote: > >> http://www.highlandtechnology.com/DSS/T346DS.html >> >> This uses an FPGA clocked at 128 MHz, a 32-bit phase accumulator, a >> 4096 point sine lookup table, and a 14 bit DAC per channel. It makes >> sines from 0 to 32 MHz with 0.015 Hz frequency resolution. It's a >> textbook DDS design, but with phase-rotation adders in the lookup >> table address paths and multipliers for amplitude. There are also >> adders into the accumulator inputs to allow FM and chirps and such. > >Nice. For sine wave, DDS is a good idea. But when you generate a square >wave with your device with e.g. 31.7 MHz, what is your maximum >cycle-to-cycle jitter? The square wave jitter is always one clock p-p, namely 8 ns. I didn't believe this, but one of my guys, who's a lot smarter than I am, convinced me. Making a square wave does violate the Nyquist criterion, which is why the waveform reproduction is imperfect. Sine waves are theoretically perfect even at high/oddball frequencies, imperfect only because of quantization and using imperfect filters, and the dac sinc thing. That Nyquist/Shannon stuff is amazing. John >BTW: Where can I buy your devices and do you have a price list on your >webpage? Email me for manuals or more info. jjlarkin atsign highlandtechnology dotcom.
From: John Larkin on 14 May 2010 11:32
On Fri, 14 May 2010 07:03:33 -0700, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Fri, 14 May 2010 07:12:06 +0200, Frank Buss <fb(a)frank-buss.de> >wrote: > >>John Larkin wrote: >> >>> http://www.highlandtechnology.com/DSS/T346DS.html >>> >>> This uses an FPGA clocked at 128 MHz, a 32-bit phase accumulator, a >>> 4096 point sine lookup table, and a 14 bit DAC per channel. It makes >>> sines from 0 to 32 MHz with 0.015 Hz frequency resolution. It's a >>> textbook DDS design, but with phase-rotation adders in the lookup >>> table address paths and multipliers for amplitude. There are also >>> adders into the accumulator inputs to allow FM and chirps and such. >> >>Nice. For sine wave, DDS is a good idea. But when you generate a square >>wave with your device with e.g. 31.7 MHz, what is your maximum >>cycle-to-cycle jitter? > >The square wave jitter is always one clock p-p, namely 8 ns. I didn't >believe this, but one of my guys, who's a lot smarter than I am, >convinced me. Making a square wave does violate the Nyquist criterion, >which is why the waveform reproduction is imperfect. Sine waves are >theoretically perfect even at high/oddball frequencies, imperfect only >because of quantization and using imperfect filters, and the dac sinc >thing. That Nyquist/Shannon stuff is amazing. Oh, if you mathematically bandlimit the samples before you put them into the lookup table, you can make a square wave (granted, with finite rise and fall times) that has way under one-clock jitter, limited mainly by dac quantization and lowpass filter perfection. Shaping the transition of the samples also allows pulse widths, or any other waveform, to be created with way under one-clock resolution. It makes Nyquist and Shannon happy again. John |