Freq. Independent Phase Shifter
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From: Jeroen on 14 May 2010 12:05 On 05/14/2010 04:03 PM, John Larkin wrote: > On Fri, 14 May 2010 07:12:06 +0200, Frank Buss<fb(a)frank-buss.de> > wrote: >> Nice. For sine wave, DDS is a good idea. But when you generate a square >> wave with your device with e.g. 31.7 MHz, what is your maximum >> cycle-to-cycle jitter? > > The square wave jitter is always one clock p-p, namely 8 ns. If you square up the sinewave output, the jitter is much less than one clock. It may seem a bit odd to filter the output down to a sine, only to square it up again afterwards, but it *does* get you a much lower jitter square. Jeroen Belleman
From: John Larkin on 14 May 2010 12:50 On Fri, 14 May 2010 18:05:30 +0200, Jeroen <jeroen(a)nospam.please> wrote: >On 05/14/2010 04:03 PM, John Larkin wrote: >> On Fri, 14 May 2010 07:12:06 +0200, Frank Buss<fb(a)frank-buss.de> >> wrote: >>> Nice. For sine wave, DDS is a good idea. But when you generate a square >>> wave with your device with e.g. 31.7 MHz, what is your maximum >>> cycle-to-cycle jitter? >> >> The square wave jitter is always one clock p-p, namely 8 ns. > >If you square up the sinewave output, the jitter is much less >than one clock. It may seem a bit odd to filter the output down >to a sine, only to square it up again afterwards, but it *does* >get you a much lower jitter square. > >Jeroen Belleman Right; if you don't violate the Sampling Theorem, waveform reproduction is theoretically perfect. Jitter becomes limited by dac quantization and filter perfection, so can be a tiny fraction of the clock period. John
From: Frank Buss on 14 May 2010 13:25 John Larkin wrote: > The square wave jitter is always one clock p-p, namely 8 ns. I didn't > believe this, but one of my guys, who's a lot smarter than I am, > convinced me. This is standard for a DDS with an accumulator, and not good, if you generate high frequency signals. E.g. for 31.7 MHz output you have a period of 31 ns, so this means 25% jitter for the worst case (of course, if you can devide the 128 MHz without rest by the selected output frequency, jitter would be near zero). But I like the idea to square up the sinewave output. Is this possible for a wide frequency range output? >>BTW: Where can I buy your devices and do you have a price list on your >>webpage? > > Email me for manuals or more info. jjlarkin atsign highlandtechnology > dotcom. I was just curious, but I guess it is a 4 digit price, too much for me for using it for my electronics hobby :-) Any reason why you don't offer it in a shop, like I can buy and compare e.g. HP signal generators? -- Frank Buss, fb(a)frank-buss.de http://www.frank-buss.de, http://www.it4-systems.de
From: John Larkin on 14 May 2010 16:26 On Fri, 14 May 2010 19:25:09 +0200, Frank Buss <fb(a)frank-buss.de> wrote: >John Larkin wrote: > >> The square wave jitter is always one clock p-p, namely 8 ns. I didn't >> believe this, but one of my guys, who's a lot smarter than I am, >> convinced me. > >This is standard for a DDS with an accumulator, and not good, if you >generate high frequency signals. E.g. for 31.7 MHz output you have a period >of 31 ns, so this means 25% jitter for the worst case (of course, if you >can devide the 128 MHz without rest by the selected output frequency, >jitter would be near zero). > >But I like the idea to square up the sinewave output. Is this possible for >a wide frequency range output? Yes. I addressed that issue in another post. As long as you don't violate the Sampling Theorem, jitter will be low. > >>>BTW: Where can I buy your devices and do you have a price list on your >>>webpage? >> >> Email me for manuals or more info. jjlarkin atsign highlandtechnology >> dotcom. > >I was just curious, but I guess it is a 4 digit price, too much for me for >using it for my electronics hobby :-) Any reason why you don't offer it in >a shop, like I can buy and compare e.g. HP signal generators? The niche we go for is lots of synchronized channels, for machinery simulation and such. There aren't many many-channel generators around. We can connect these boxes and generate unlimited numbers of synchronized/phase shifted/swept/ratioed waveforms. One of our customers has several 64-channel setups, for simulating jet engines into engine control computers. John
From: krw on 14 May 2010 18:57
On Thu, 13 May 2010 21:24:27 -0700, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Thu, 13 May 2010 20:52:25 -0700, Winston <Winston(a)bigbrother.net> >wrote: > >>On 5/13/2010 6:57 PM, John Larkin wrote: >> >>(...) >> >>> Not exactly. If you address the sine lookup table with a >>> fixed-frequency-clocked phase accumulator, instead of a counter, you >>> can tune the sine frequency to as fine a resolution as you want, just >>> by using more bits in the accumulator. >> >>(...) >> >>So the Phase Accumulator itself is a state machine which creates >>a binary version of the next point to be output predicated on >>the previous point and the frequency control word. >> >>It is starting to soak in. Thanks! >> >>--Winston >> > >I guess. > >Imagine a 32-bit clockable binary register, just 32 D-type flipflops. >Call the value in the register R. Every clock, add a 32-bit value F to >it. so > >At every clock > > R = R + F > >F is our 32-bit frequency set register. > >If R=1, it will take 2^32 clocks for R to make a full cycle back to >where it started. If R=2, it will cycle around in 2^31 clocks. > >Take the 12 most significant bits of the R register and use them to >address a sinewave lookup table, and use the result to load a DAC at >the same clock rate. > >What's cool is that you can put all sorts of values into F, and the >frequency of the DAC is proportional to the value F. For small values >of F, it will take many clocks before you bump the upper 12 bits and >advance one location in the lookup table. As F gets bigger, you'll >start hopping around the table in bigger jumps, skipping some entries. >But if you lowpass filter the DAC output, you always get a sine wave. >The frequency-set resolution is Fclk/2^32, which is pretty fine. If >you use a 64-bit register, resolution is Fclk/2^64. > >It's really very simple, an easy to build in an FPGA. That's pretty much what I did for a CCD shutter motor controller for a high def color camera a couple of years ago. The accumulator drove three lookups to drive the three-phase motor outputs. In normal mode the thing ran open loop with the 'F' register setting the RPM. An optical encoder was used to sense position (and RPM). During start-up and if the motor wasn't where it should be (acceleration needed), the 'F' register was set to the encoder value (position) plus a constant until the RPM hit a threshold. Didn't take much of a Virtex-4. Timing wasn't hard to meet either. ;-) |