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From: de4 on 18 Feb 2010 07:12
>On Wed, 17 Feb 2010 17:55:07 -0600, "de4"
<de4(a)n_o_s_p_a_m.poczta.onet.pl>
>wrote:
>
>>Hello !
>>
>>I have a very big problem. I created a simple procesor and on simulation
it
>>works fine, on step mode it works fine but when it is running on full
speed
>>of clock it got crazy... :
>
>>are there any other constraint useful for me ? Can it be constraint fault
?
>>Or it must be design problem ? Or something else ? 16Mhz clock is
>>connected to FPGA.
>
>16MHz is slow enough that problems meeting timing are unlikely.
>
>Is the processor accessing any memory external to the FPGA, or just thu
internal
>BRAMs? External memory is a likely source of timing problems.
>
>Check for any inputs to the processor that aren't themselves clocked by
the same
>clock, and eliminate them (by reclocking them from the CPU clock.
>
>- Brian
>


Thank you for response...

Processor don't accessing external memory only BlockRAM based RAM.
I have one input in my system that is a clock connected to global clock.
this input is (clock signal) connected to processor, ram and I/O ( uses TX
and RX line to communicate with processor from outside). Processor is
connected with Clock, Reset and RAM signals. RAM is connected with Clock,
Processor and to I/O unit (dual port). To I/O unit is connected clock,
Reset and signal from ram and TX,RX lines.

I writing because it is strage behavior I even could say that it is
randomly...
If something would be wrongly design (I mean some fsm in control unit)
program would be executed badly but always in the same way... In my case
some times is
PC values are 0, 1 ,2 ,4, 5 some times it is 0, 1 and stops.
16 Mhz is not too much...

Best regards,
Maciek




---------------------------------------
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From: Symon on 18 Feb 2010 07:37
On 2/18/2010 12:12 PM, de4 wrote:
>
> I writing because it is strage behavior I even could say that it is
> randomly...
> If something would be wrongly design (I mean some fsm in control unit)
> program would be executed badly but always in the same way... In my case
> some times is
> PC values are 0, 1 ,2 ,4, 5 some times it is 0, 1 and stops.
> 16 Mhz is not too much...
>
> Best regards,
> Maciek
>
Hi Maciek,
Can you use chipscope to look at the signals which control the program
counter, and the PC's value?
Do you get any warnings from P&R something like "Warning: Signal clock
connects to non-clock resource"?

Look in all the report files for any warnings to do with your clock signal.

Does your reset get released synchronously to the clock?

HTH, Syms.
From: de4 on 18 Feb 2010 08:11
>Hi Maciek,
>Can you use chipscope to look at the signals which control the program
>counter, and the PC's value?
>Do you get any warnings from P&R something like "Warning: Signal clock
>connects to non-clock resource"?
>
>Look in all the report files for any warnings to do with your clock
signal.
>
>Does your reset get released synchronously to the clock?
>
>HTH, Syms.
>

Chipscope is beyond my possibilities... I program FPGA using Avnet Programm
and I don't have Platform Cable... In PAR I don't have any warnings at
all...
I will search them but I didn't see any warnings.

Sorry but "Does your reset get released synchronously to the clock?"
I don;t understand this - I have some Dff like this :

entity D_FF is
port( D, Clock, Reset : in STD_LOGIC;
Q, notQ : out STD_LOGIC);
end D_FF;

architecture CPU of D_FF is
signal Qout : STD_LOGIC;
begin

PROCESS(D, Clock, Reset)
BEGIN
IF Reset = '1' THEN -- Don't wait for clock
Q <= '0';
notQ <= '1';
ELSIF (Clock'event) AND (Clock='1') THEN -- Positive Edge
Q <= D;
notQ <= not D;
END IF;
END PROCESS;

end CPU;


and this reset is connected to button on a board...
So I think rather not...

Thank you for response...

---------------------------------------
Posted through http://www.FPGARelated.com
From: Symon on 18 Feb 2010 10:55
On 2/18/2010 1:11 PM, de4 wrote:
>>
> PROCESS(D, Clock, Reset)
> BEGIN
> IF Reset = '1' THEN -- Don't wait for clock
> Q<= '0';
> notQ<= '1';
> ELSIF (Clock'event) AND (Clock='1') THEN -- Positive Edge
> Q<= D;
> notQ<= not D;
> END IF;
> END PROCESS;
>
> end CPU;
>
>
> and this reset is connected to button on a board...
> So I think rather not...
>
Hi,
So, it probably isn't the problem, but why is 'D' in your sensitivity list?

You should build a debounce circuit for the reset button that is
synchronous to your clock.

http://en.wikipedia.org/wiki/Switch#Contact_bounce

HTH., Syms.
From: Symon on 18 Feb 2010 10:59
Also

http://www.xilinx.com/support/documentation/white_papers/wp272.pdf
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