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From: de4 on 18 Feb 2010 11:51
>Also
>
>http://www.xilinx.com/support/documentation/white_papers/wp272.pdf
>

Okey I will try it, I only wondering if those papers telling about
problems with debouncing and does it refers also to capacity switches ?

About case why D in on sensitivity list - I must tell I don't now, I will
remove it from there...

Thank you for intresting in my stupid case,
I will try trick with debounce and will see...

Once again thank you for ideas :)

Best Regards,
Maciek

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From: Mike Harrison on 18 Feb 2010 12:49
On Wed, 17 Feb 2010 17:55:07 -0600, "de4" <de4(a)n_o_s_p_a_m.poczta.onet.pl> wrote:

>Hello !
>
>I have a very big problem. I created a simple procesor and on simulation it
>works fine, on step mode it works fine but when it is running on full speed
>of clock it got crazy... :( It should execute instruction i order
>0.1.2.3.4.5 (Program Counter values and PC is connected to leds) and it
>executes sometimes 0.1.3.5 some times 0.1.2.3.4.5.6.7.8.9 or 0.1.2.6.3.4 or
>0.1 or sometimes it is as it should. Sometimes it stops suddenly executing
>or executing too much. It is written in VHDL on Spartan 3A. It is too big
>to show it here but maybe some experts will be able to tell me what is
>going on... I have constraints like this in UCF file :
>
>NET "Clock" LOC = C10;
>NET "Clock" IOSTANDARD = LVCMOS33;
>NET "Clock" PERIOD = 62.5ns HIGH 50%;
>NET "Reset" LOC = H4;
>NET "Reset" IOSTANDARD = LVCMOS33;
>NET "TX" LOC = B3;
>NET "TX" IOSTANDARD = LVCMOS33;
>NET "RX" LOC = A3;
>NET "RX" IOSTANDARD = LVCMOS33;
>
>are there any other constraint useful for me ? Can it be constraint fault ?
>Or it must be design problem ? Or something else ? 16Mhz clock is
>connected to FPGA. It works OK using step by step mode but on full speed
>it's stragne bevahior... I really need help, I trying to solve it for three
>days and nothing...
>
>Thank you all for any answers...
>
>---------------------------------------
>Posted through http://www.FPGARelated.com

Have you tried running at a lower clock rate?
This would seem a simple way of determining if it is a per-cycle overall path delay type thing or a
setup/hold, race condition etc. due to internal propagation times.
From: jc on 19 Feb 2010 07:38
> >NET "Clock" PERIOD = 62.5ns HIGH 50%;
> Have you tried running at a  lower clock rate?

Just to be devil's advocate, it still seems as if timing/skew is not
met, although you have indicated otherwise (1 - PERIOD=62.5ns, 2 - no
timing errors). Can you configure the STA tool to list the longest
routes (even though they are passing), just to get an idea that it is
being measured for the 16 MHz? In other words, prove that design is
being timed to 16 MHz.
From: de4 on 19 Feb 2010 16:59
>Also
>
>http://www.xilinx.com/support/documentation/white_papers/wp272.pdf
>

I read those documents and I stared to looking at does resets.
I've changed all D flip flops. Now they are reset synch. because asynch.
reset is a bad practice. In document wp272 I read that I don't need global
reset at all. But I notice two things.

1. When I reconfigure FPGA and don't touch anything on a board procesor
executes program wrongly. When executing is finished and I resert procesor
it executes program in good way.

2. When I reconfigure FPGA and I will hold reset button until download
process will be finished and I will realase button it executes good also.

Where can be a problem ? Should I use some GSR net ? I heard it is not good
solution also... If I should what is best practise ? Or maybe some setting
in CoreGen (ram) are bad - I don't use any EN oraz RST pins in my
design...

Thank you for any response.

Regards,
Maciek





---------------------------------------
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From: Symon on 20 Feb 2010 12:25
On 2/19/2010 9:59 PM, de4 wrote:
>
> 1. When I reconfigure FPGA and don't touch anything on a board procesor
> executes program wrongly. When executing is finished and I resert procesor
> it executes program in good way.
>
> 2. When I reconfigure FPGA and I will hold reset button until download
> process will be finished and I will realase button it executes good also.
>
> Where can be a problem ? Should I use some GSR net ? I heard it is not good
> solution also... If I should what is best practise ? Or maybe some setting
> in CoreGen (ram) are bad - I don't use any EN oraz RST pins in my
> design...
>
Hi Maciek,
It sounds as though some state machine in your design is set to the
proper initial conditions when the FPGA is loaded. You should be able to
find this with simulation.
HTH., Syms.
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