Prev: How a state machine is constructed using latches?
Next: Derived clock violation in Virtex4
From: -jg on 20 Feb 2010 17:55
On Feb 20, 10:59 am, "de4" <de4(a)n_o_s_p_a_m.poczta.onet.pl> wrote:
> 1. When I reconfigure FPGA and don't touch anything on a board procesor
> executes program wrongly. When executing is finished and I resert procesor
> it executes program in good way.
>
> 2. When I reconfigure FPGA and I will hold reset button until download
> process will be finished and I will realase button it executes good also.

That sounds like your Reset, and the Config-Exit are not quite the
same thing.

Most uC have a POR exit State-timer, that asserts reset for a few
cycles. (Some may also delay reasonable times to allow Xtal Osc
startup etc )

So rather than hope config-exit duplicates your reset, why not try
the add of small logic that generates a signal you OR into your reset-
button path ?
From: rickman on 20 Feb 2010 21:03
On Feb 19, 4:59 pm, "de4" <de4(a)n_o_s_p_a_m.poczta.onet.pl> wrote:
> >Also
>
> >http://www.xilinx.com/support/documentation/white_papers/wp272.pdf
>
> I read those documents and I stared to looking at does resets.
> I've changed all D flip flops. Now they are reset synch. because asynch.
> reset is a bad practice. In document wp272 I read that I don't need global
> reset at all. But I notice two things.
>
> 1. When I reconfigure FPGA and don't touch anything on a board procesor
> executes program wrongly. When executing is finished and I resert procesor
> it executes program in good way.
>
> 2. When I reconfigure FPGA and I will hold reset button until download
> process will be finished and I will realase button it executes good also.
>
> Where can be a problem ? Should I use some GSR net ? I heard it is not good
> solution also... If I should what is best practise ? Or maybe some setting
> in CoreGen (ram) are bad - I don't use any EN oraz RST pins in my
> design...

It sounds to me like your reset is not being asserted when you
reconfigure. I think Symon meant to say your initial conditions are
*not* being set when you configure the device.

Personally, I have no trouble using the async reset. I just make sure
all of my logic is capable of either starting correctly on an async
reset (like adding a short shift register to qualify the reset) or
verifying that the logic is waiting for some external event to start
or even for it to "recover" if started badly like a state machine.

Rick
First  |  Prev  | 
Pages: 1 2 3 4
Prev: How a state machine is constructed using latches?
Next: Derived clock violation in Virtex4