divide by 25/16
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From: colin on 14 Aug 2006 19:56 "John Popelish" <jpopelish(a)rica.net> wrote in message news:yLCdnS-F2clLlHzZnZ2dnUVZ_r6dnZ2d(a)adelphia.com... > How about dividing by a symmetrical output factor of 25 (1.875 MHz > output), and then use a rather modest pll to multiply that frequency > by 16. Although that would give the right output, it would limit the input range by the range of the vco and is probably a bit more complicated, idealy i just want to lose 9 out of every 25 input pulses, hopefully with just a few logic ics. preferably not to lose all nine one after the other but thats just me being a perfectionist. Colin =^.^=
From: APR on 14 Aug 2006 20:07 "Tim Wescott" <tim(a)seemywebsite.com> wrote in message news:VqGdnSXQd__-lXzZnZ2dnUVZ_ridnZ2d(a)web-ster.com... > Jim Thompson wrote: > >> On Mon, 14 Aug 2006 22:46:43 GMT, "colin" >> <no.spam.for.me(a)ntlworld.com> wrote: >> >> >>>Hi, >>>I need a circuit to divide a <50mhz digital signal by 25/16. >>>ie. i need to lose 9 out of every 25 pulses. >>>Is there a simple/standard way to do this ? >>> >>>Ive come up with a few ideas that use quite a lot of logic, >>>such as a divide the input by 25 with 1-25 decoder wich then swallows a >>>pulse at the apropriate count. >>> >>>or divide by 16 on the output wich swallows a pulse every other count and >>>also at terminal count. >>>but it runs into trouble becuse it swallows its own clock pulses and >>>doesnt >>>advance. >>> >>>or invert the clock input to a flip flop with an xor from its output, >>>wich >>>gives a nice looking pulse train >>>but needs a few more pulses taken out. >>> >>>Its to go after a 3ghz divide by 64 prescaler so the combined divide is >>>100. >>> >>>Colin =^.^= >>> >> >> >> 25/16 is unusual. Usually it's 15/16 or 7/8, etc. Surf on "dual >> modulus pre-scaler". >> >> ...Jim Thompson > > No, he doesn't want 25 _or_ 16, he wants twenty five sixteenths. > I thing his intention is to have sixteen twentyfifths, he wants to "divide by 25/16" or multiply by 16/25
From: John Popelish on 14 Aug 2006 20:18 colin wrote: > "John Popelish" <jpopelish(a)rica.net> wrote in message > news:yLCdnS-F2clLlHzZnZ2dnUVZ_r6dnZ2d(a)adelphia.com... > >>How about dividing by a symmetrical output factor of 25 (1.875 MHz >>output), and then use a rather modest pll to multiply that frequency >>by 16. > > > Although that would give the right output, it would limit the input range by > the range of the vco and is probably a bit more complicated, idealy i just > want to lose 9 out of every 25 input pulses, hopefully with just a few logic > ics. > > preferably not to lose all nine one after the other but thats just me being > a perfectionist. I wonder if the 7497 is available in a fast enough logic family. http://www-s.ti.com/sc/ds/sn7497.pdf
From: Jim Thompson on 14 Aug 2006 20:24 On Mon, 14 Aug 2006 20:18:13 -0400, John Popelish <jpopelish(a)rica.net> wrote: >colin wrote: >> "John Popelish" <jpopelish(a)rica.net> wrote in message >> news:yLCdnS-F2clLlHzZnZ2dnUVZ_r6dnZ2d(a)adelphia.com... >> >>>How about dividing by a symmetrical output factor of 25 (1.875 MHz >>>output), and then use a rather modest pll to multiply that frequency >>>by 16. >> >> >> Although that would give the right output, it would limit the input range by >> the range of the vco and is probably a bit more complicated, idealy i just >> want to lose 9 out of every 25 input pulses, hopefully with just a few logic >> ics. >> >> preferably not to lose all nine one after the other but thats just me being >> a perfectionist. > >I wonder if the 7497 is available in a fast enough logic family. >http://www-s.ti.com/sc/ds/sn7497.pdf I was going to suggest rate multipliers but you beat me to it. You might have to roll your own out of PECL. ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
From: colin on 14 Aug 2006 20:35
"APR" <I_Don't_Want_Spam(a)NoSpam.com> wrote in message news:44e1107b(a)dnews.tpgi.com.au... > > "Tim Wescott" <tim(a)seemywebsite.com> wrote in message > news:VqGdnSXQd__-lXzZnZ2dnUVZ_ridnZ2d(a)web-ster.com... > > Jim Thompson wrote: > > > >> On Mon, 14 Aug 2006 22:46:43 GMT, "colin" > >> <no.spam.for.me(a)ntlworld.com> wrote: > >> > >> > >>>Hi, > >>>I need a circuit to divide a <50mhz digital signal by 25/16. > >>>ie. i need to lose 9 out of every 25 pulses. > >>>Is there a simple/standard way to do this ? > >>> > >>>Ive come up with a few ideas that use quite a lot of logic, > >>>such as a divide the input by 25 with 1-25 decoder wich then swallows a > >>>pulse at the apropriate count. > >>> > >>>or divide by 16 on the output wich swallows a pulse every other count and > >>>also at terminal count. > >>>but it runs into trouble becuse it swallows its own clock pulses and > >>>doesnt > >>>advance. > >>> > >>>or invert the clock input to a flip flop with an xor from its output, > >>>wich > >>>gives a nice looking pulse train > >>>but needs a few more pulses taken out. > >>> > >>>Its to go after a 3ghz divide by 64 prescaler so the combined divide is > >>>100. > >>> > >>>Colin =^.^= > >>> > >> > >> > >> 25/16 is unusual. Usually it's 15/16 or 7/8, etc. Surf on "dual > >> modulus pre-scaler". > >> > >> ...Jim Thompson > > > > No, he doesn't want 25 _or_ 16, he wants twenty five sixteenths. > > > I thing his intention is to have sixteen twentyfifths, he wants to "divide > by 25/16" or multiply by 16/25 > yes I want sixteen twentyfiths of the input frequency or x 0.64 oh hey hang on but thats the same as dividing by twenty five sixteenths wich is divide by 1.562, so you both right. 25/16 is just the smallest rational fraction. its what you need to add on to a divide by 64 prescaler to get it to a nice round decimal divide by 100. Colin =^.^= |