divide by 25/16
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From: colin on 14 Aug 2006 18:46 Hi, I need a circuit to divide a <50mhz digital signal by 25/16. ie. i need to lose 9 out of every 25 pulses. Is there a simple/standard way to do this ? Ive come up with a few ideas that use quite a lot of logic, such as a divide the input by 25 with 1-25 decoder wich then swallows a pulse at the apropriate count. or divide by 16 on the output wich swallows a pulse every other count and also at terminal count. but it runs into trouble becuse it swallows its own clock pulses and doesnt advance. or invert the clock input to a flip flop with an xor from its output, wich gives a nice looking pulse train but needs a few more pulses taken out. Its to go after a 3ghz divide by 64 prescaler so the combined divide is 100. Colin =^.^=
From: Jim Thompson on 14 Aug 2006 18:52 On Mon, 14 Aug 2006 22:46:43 GMT, "colin" <no.spam.for.me(a)ntlworld.com> wrote: >Hi, >I need a circuit to divide a <50mhz digital signal by 25/16. >ie. i need to lose 9 out of every 25 pulses. >Is there a simple/standard way to do this ? > >Ive come up with a few ideas that use quite a lot of logic, >such as a divide the input by 25 with 1-25 decoder wich then swallows a >pulse at the apropriate count. > >or divide by 16 on the output wich swallows a pulse every other count and >also at terminal count. >but it runs into trouble becuse it swallows its own clock pulses and doesnt >advance. > >or invert the clock input to a flip flop with an xor from its output, wich >gives a nice looking pulse train >but needs a few more pulses taken out. > >Its to go after a 3ghz divide by 64 prescaler so the combined divide is 100. > >Colin =^.^= > 25/16 is unusual. Usually it's 15/16 or 7/8, etc. Surf on "dual modulus pre-scaler". ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
From: colin on 14 Aug 2006 19:24 "Jim Thompson" <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote in message news:1jv1e2pqeheuh9lv4in0n7i55s1kd4ba4i(a)4ax.com... > On Mon, 14 Aug 2006 22:46:43 GMT, "colin" > <no.spam.for.me(a)ntlworld.com> wrote: > > >Hi, > >I need a circuit to divide a <50mhz digital signal by 25/16. > >ie. i need to lose 9 out of every 25 pulses. > >Is there a simple/standard way to do this ? > > > >Ive come up with a few ideas that use quite a lot of logic, > >such as a divide the input by 25 with 1-25 decoder wich then swallows a > >pulse at the apropriate count. > > > >or divide by 16 on the output wich swallows a pulse every other count and > >also at terminal count. > >but it runs into trouble becuse it swallows its own clock pulses and doesnt > >advance. > > > >or invert the clock input to a flip flop with an xor from its output, wich > >gives a nice looking pulse train > >but needs a few more pulses taken out. > > > >Its to go after a 3ghz divide by 64 prescaler so the combined divide is 100. > > > >Colin =^.^= > > > > 25/16 is unusual. Usually it's 15/16 or 7/8, etc. Surf on "dual > modulus pre-scaler". > > ...Jim Thompson Thanks, im familiar with dual modulus prescalers but usualy only seen them within PLL chips, I think they divide by either of the 2 ratios one of wich is 1 higher so that a single count can be swallowed by switching to the higher modulus. I found it a bit confusing when I first came accros it, you end up with illegal divide ratios etc. However I need divide by 25/16 ie 1.5625 not divide by 25 or 16. so im not sure they will work, unless they can replace the /64 prescaler completly. At the moment Im using a 3ghz PLL chip as a /100 prescaler but needs to be programed each time, shame /100 3ghz prescalers dont seem to be available, I could live with the /64 and work out the real frequency but id rather make it easier. Colin =^.^=
From: Tim Wescott on 14 Aug 2006 19:33 Jim Thompson wrote: > On Mon, 14 Aug 2006 22:46:43 GMT, "colin" > <no.spam.for.me(a)ntlworld.com> wrote: > > >>Hi, >>I need a circuit to divide a <50mhz digital signal by 25/16. >>ie. i need to lose 9 out of every 25 pulses. >>Is there a simple/standard way to do this ? >> >>Ive come up with a few ideas that use quite a lot of logic, >>such as a divide the input by 25 with 1-25 decoder wich then swallows a >>pulse at the apropriate count. >> >>or divide by 16 on the output wich swallows a pulse every other count and >>also at terminal count. >>but it runs into trouble becuse it swallows its own clock pulses and doesnt >>advance. >> >>or invert the clock input to a flip flop with an xor from its output, wich >>gives a nice looking pulse train >>but needs a few more pulses taken out. >> >>Its to go after a 3ghz divide by 64 prescaler so the combined divide is 100. >> >>Colin =^.^= >> > > > 25/16 is unusual. Usually it's 15/16 or 7/8, etc. Surf on "dual > modulus pre-scaler". > > ...Jim Thompson No, he doesn't want 25 _or_ 16, he wants twenty five sixteenths. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.html
From: John Popelish on 14 Aug 2006 19:48
colin wrote: > "Jim Thompson" <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote in > message news:1jv1e2pqeheuh9lv4in0n7i55s1kd4ba4i(a)4ax.com... > >>On Mon, 14 Aug 2006 22:46:43 GMT, "colin" >><no.spam.for.me(a)ntlworld.com> wrote: >> >> >>>Hi, >>>I need a circuit to divide a <50mhz digital signal by 25/16. >>>ie. i need to lose 9 out of every 25 pulses. >>>Is there a simple/standard way to do this ? >>> >>>Ive come up with a few ideas that use quite a lot of logic, >>>such as a divide the input by 25 with 1-25 decoder wich then swallows a >>>pulse at the apropriate count. >>> >>>or divide by 16 on the output wich swallows a pulse every other count and >>>also at terminal count. >>>but it runs into trouble becuse it swallows its own clock pulses and > > doesnt > >>>advance. >>> >>>or invert the clock input to a flip flop with an xor from its output, > > wich > >>>gives a nice looking pulse train >>>but needs a few more pulses taken out. >>> >>>Its to go after a 3ghz divide by 64 prescaler so the combined divide is > > 100. > >>>Colin =^.^= >>> >> >>25/16 is unusual. Usually it's 15/16 or 7/8, etc. Surf on "dual >>modulus pre-scaler". >> >> ...Jim Thompson > > > Thanks, im familiar with dual modulus prescalers but usualy only seen them > within PLL chips, > I think they divide by either of the 2 ratios one of wich is 1 higher > so that a single count can be swallowed by switching to the higher modulus. > I found it a bit confusing when I first came accros it, you end up with > illegal divide ratios etc. > > However I need divide by 25/16 ie 1.5625 not divide by 25 or 16. so im not > sure they will work, unless they can replace the /64 prescaler completly. > > At the moment Im using a 3ghz PLL chip as a /100 prescaler but needs to be > programed each time, shame /100 3ghz prescalers dont seem to be available, I > could live with the /64 and work out the real frequency but id rather make > it easier. > > Colin =^.^= > > How about dividing by a symmetrical output factor of 25 (1.875 MHz output), and then use a rather modest pll to multiply that frequency by 16. |