divide by 25/16
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From: jpopelish on 15 Aug 2006 21:17 colin wrote: > "John Popelish" wrote: > > How about dividing by a symmetrical output factor of 25 (1.875 MHz > > output), and then use a rather modest pll to multiply that frequency > > by 16. > > Although that would give the right output, it would limit the input range by > the range of the vco ... What range do you need for the 3 gHz? 2 to 4 gHz ? That shouldn't be hard to cover (20 to 40 MHz oscillator), unless the frequency is going to change very quickly.
From: Don Lancaster on 17 Aug 2006 18:27 colin wrote: > "APR" <I_Don't_Want_Spam(a)NoSpam.com> wrote in message > news:44e1107b(a)dnews.tpgi.com.au... > >>"Tim Wescott" <tim(a)seemywebsite.com> wrote in message >>news:VqGdnSXQd__-lXzZnZ2dnUVZ_ridnZ2d(a)web-ster.com... >> >>>Jim Thompson wrote: >>> >>> >>>>On Mon, 14 Aug 2006 22:46:43 GMT, "colin" >>>><no.spam.for.me(a)ntlworld.com> wrote: >>>> >>>> >>>> >>>>>Hi, >>>>>I need a circuit to divide a <50mhz digital signal by 25/16. >>>>>ie. i need to lose 9 out of every 25 pulses. >>>>>Is there a simple/standard way to do this ? >>>>> >>>>>Ive come up with a few ideas that use quite a lot of logic, >>>>>such as a divide the input by 25 with 1-25 decoder wich then swallows a >>>>>pulse at the apropriate count. >>>>> >>>>>or divide by 16 on the output wich swallows a pulse every other count > > and > >>>>>also at terminal count. >>>>>but it runs into trouble becuse it swallows its own clock pulses and >>>>>doesnt >>>>>advance. >>>>> >>>>>or invert the clock input to a flip flop with an xor from its output, >>>>>wich >>>>>gives a nice looking pulse train >>>>>but needs a few more pulses taken out. >>>>> >>>>>Its to go after a 3ghz divide by 64 prescaler so the combined divide is >>>>>100. >>>>> >>>>>Colin =^.^= >>>>> >>>> >>>> >>>>25/16 is unusual. Usually it's 15/16 or 7/8, etc. Surf on "dual >>>>modulus pre-scaler". >>>> >>>> ...Jim Thompson >>> >>>No, he doesn't want 25 _or_ 16, he wants twenty five sixteenths. >>> >> >>I thing his intention is to have sixteen twentyfifths, he wants to "divide >>by 25/16" or multiply by 16/25 >> > > > yes I want sixteen twentyfiths of the input frequency or x 0.64 > oh hey hang on but thats the same as dividing by twenty five sixteenths > wich is divide by 1.562, so you both right. > > 25/16 is just the smallest rational fraction. > > its what you need to add on to a divide by 64 prescaler to get it to a nice > round decimal divide by 100. > > Colin =^.^= > > A phase lock loop, of course. -- Many thanks, Don Lancaster voice phone: (928)428-4073 Synergetics 3860 West First Street Box 809 Thatcher, AZ 85552 rss: http://www.tinaja.com/whtnu.xml email: don(a)tinaja.com Please visit my GURU's LAIR web site at http://www.tinaja.com
From: Ancient_Hacker on 17 Aug 2006 18:39 how about a 4-bit synchronous counter (75AHC161?), when it overflows, it sets a D flip flop which enables a 74AHC4017 to count up to 9, then have it's 9 output reset the FF? The D flip flp's not-Q output gates the signal.
From: Joop on 17 Aug 2006 19:01 > >aha yes that would do, many thanks, shld be able to do in 2 chips a 74'390 >dual decade counter and a 74'00. > >I had written down the numbers in base 5, and had a big page of possible >sequences looking for easy decodes, I think I just about had this sequence >but didnt see the wood for the trees and overlooked its simplicity, im >impresed at ariving at this so quickly :) > >Colin =^.^= > I actually have such a device. It is a :100 prescaler using the 74LS390 after a U664 1.2GHz :64 counter. Apparently it was based on a Siemens appnote. Basically there are two 5/4 counters cascaded. An LS02 is used next to the LS390. The input at pin 12 is also fed via an inverter and norred with pin 9. The output goes into pin 4. Pin 4 is inverted and norred with pin 7. This nor output is your :100 signal. Cheers. Joop
From: colin on 18 Aug 2006 10:01
"Joop" <jojo(a)chello.nl> wrote in message news:tss9e2d8q3dtl6587k1lsvkgp1jshmsihg(a)4ax.com... > > > > >aha yes that would do, many thanks, shld be able to do in 2 chips a 74'390 > >dual decade counter and a 74'00. > > > >I had written down the numbers in base 5, and had a big page of possible > >sequences looking for easy decodes, I think I just about had this sequence > >but didnt see the wood for the trees and overlooked its simplicity, im > >impresed at ariving at this so quickly :) > > > >Colin =^.^= > > > I actually have such a device. It is a :100 prescaler using the > 74LS390 after a U664 1.2GHz :64 counter. > > Apparently it was based on a Siemens appnote. Basically there are two > 5/4 counters cascaded. > An LS02 is used next to the LS390. The input at pin 12 is also fed via > an inverter and norred with pin 9. The output goes into pin 4. Pin 4 > is inverted and norred with pin 7. This nor output is your :100 > signal. > > Cheers. > > Joop Cool thanks, I tried to find the appnote with google but no luck Colin =^.^= |