divide by 25/16
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From: colin on 14 Aug 2006 21:53 "James Waldby" <j-waldby(a)pat7.com> wrote in message news:44E12018.27627545(a)pat7.com... > colin wrote: > ... > > I need a circuit to divide a <50mhz digital signal by 25/16. > > ie. i need to lose 9 out of every 25 pulses. > ... > > As 25/16 = (5/4)^2, if you follow a 5/4 divider by > another one, you'll have 25/16. > > -jiw oo, thats well spotted, so I need 2 circuits that each lose 1 out of 5 pulses. I wonder if that actually works out simpler than 1 that loses 9 out of 25. or did you have something in mind ? Colin =^.^=
From: colin on 14 Aug 2006 22:02 "budgie" <me(a)privacy.net> wrote in message news:ap72e2putuqjts6eb8p4b8tneogu57o0uf(a)4ax.com... > On Mon, 14 Aug 2006 22:46:43 GMT, "colin" <no.spam.for.me(a)ntlworld.com> wrote: > > >Hi, > >I need a circuit to divide a <50mhz digital signal by 25/16. > >ie. i need to lose 9 out of every 25 pulses. > >Is there a simple/standard way to do this ? > > > >Ive come up with a few ideas that use quite a lot of logic, > >such as a divide the input by 25 with 1-25 decoder wich then swallows a > >pulse at the apropriate count. > > > >or divide by 16 on the output wich swallows a pulse every other count and > >also at terminal count. > >but it runs into trouble becuse it swallows its own clock pulses and doesnt > >advance. > > > >or invert the clock input to a flip flop with an xor from its output, wich > >gives a nice looking pulse train > >but needs a few more pulses taken out. > > > >Its to go after a 3ghz divide by 64 prescaler so the combined divide is 100. > > Most swallow systems result in an irregular output waveform, which may or may > not create downstream issues (such as unwanted sidebands/spurs). fortunatly its not a problem, thanks for the headsup tho :) > I suspect you > have created a problem by your choice of /64. Can you not source some other > prescaler? well its a 3ghz+ pecl prescaler, theres not a great deal of choice at 3ghz other than 2^n binary division. > If not, you are probably looking at two cascaded dual modulus divide > by 4/5 stages, and I'm not aware of any integrated 4/5 devices. This is cuasing some confusion with the ambigous meaning of the slash, if you mean dual modulus of 4/5 these will divide by 4 or 5, I need to divide by 1.5625 (=25/16 as a fraction) wich doesnt lend itself to dual modulus. well actually a dual modulus of 2/1 is ok! Colin =^.^=
From: Mark on 14 Aug 2006 22:10 > > ... > > > I need a circuit to divide a <50mhz digital signal by 25/16. > > > ie. i need to lose 9 out of every 25 pulses. > > ... > You need to think about this carefully, as another poster mentoined, what you will get is an irregular pulse train, actually a signal that jumps back and forth beteen two frequencies that average out to your desired frequency but is never actually equal to your desired frequency. If this is OK for your application, then go for it, in many cases this is not OK. Mark
From: Ken Smith on 14 Aug 2006 22:27 In article <ebr5ph$gn$2(a)blue.rahul.net>, Ken Smith <kensmith(a)green.rahul.net> wrote: >In article <n37Eg.27268$ts3.10238(a)newsfe2-gui.ntli.net>, >colin <no.spam.for.me(a)ntlworld.com> wrote: >>Hi, >>I need a circuit to divide a <50mhz digital signal by 25/16. >>ie. i need to lose 9 out of every 25 pulses. >>Is there a simple/standard way to do this ? > >This will fit into a 22V10 so you can do it with one chip if you want. > >The dinner bell just rang. I'll be back with something not using >programable parts after dinner. Ok I'm back from dinner :> If you write out the numbers from 0 to 25 in base 5, you will discover that the lower digit is odd 10 times. Just looking at the LSB of the counter, you could skip 10 clock pulses. When the upper digit is 4, you could allow one clock for one of the odd numbers LSB A -------------------------! \ !NAND >------- Allow clock B --------------! \ --! / !NAND >-- C -- -----! / ! ... etc .. ! ! MSB H--------- -- -- kensmith(a)rahul.net forging knowledge
From: Ken Smith on 14 Aug 2006 22:32
In article <6M8Eg.41733$WY2.2516(a)newsfe3-gui.ntli.net>, colin <no.spam.for.me(a)ntlworld.com> wrote: [...] >Ah yes rate multipliers, I never realy studied their internal circuit much >till now, they always seemed confusing. Rate multipliers are easy to understand if you start with the idea of making a very bad one and then improve it like this. Given a binary counter and a binary comparitor, you can allow the clock to come out until the number in the counter hits some value and then block the count until the counter overflows. This gives a very bursty output. Now rewire the counter swapping the order of the bits so that the LSB is hooked to the MSB of the comparitor and so on. Observe how that spreads out the pulses. This is how I first got ahold of how they work. -- -- kensmith(a)rahul.net forging knowledge |