Board layout for FPGA
in [FPGA]
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From: Symon on 4 Feb 2010 05:28 On 2/4/2010 8:23 AM, David Brown wrote: > > You have a lot more experience at this sort of thing than me, Rick, so > I'm a little wary of disagreeing with you. But I'm sure you'll tell me > if I get something wrong! > > I don't see that you have to worry about any termination here. With fast > enough signal edges, you can get ringing - but that typically will not > matter because you don't sample the signals until the ringing has > subsided. > > Ringing can cause a few problems - the overshoot/undershoot can go > outside the voltage range of the pins on the line, it can cause > interference for neighbouring signals, you can't read the signal while > it is ringing, and it can cause big trouble when connected to > edge-sensitive inputs. But most of these are not going to be a problem > in your case, I think. > Dear David, Steve, Going "outside the voltage range of the pins on the line" can break the device. IIRC there are Xilinx appnotes which go into this problem in some detail; powering 3.3V with 3V was something I think they suggested! (See XAPP653) Also, the thing will probably fail any sort on electromagnetic compliance test that you would need to do before you sell this. And you are unlikely to be able to listen to 'The Archers' while this thing is in the room. To the OP, in the absence of micro-vias, I would recommend a 6 layer board. Maybe like this:- signal signal ground ground power/signal signal Keep all the layers as close together as your PCB manufacturer allows and make up the board thickness with the core between the two ground layers. Xilinx on the top. Route the powers, or use copper pours. Try to make room for bypass caps on the back of the board from the FPGA. This stack up will make it very difficult for a beginner to go wrong from an SI point of view, as ground is always near. This is particularly true if you have a nice spread of ground vias tying the two ground planes together. That doesn't mean you shouldn't simulate it with Hyperlynx, but I bet that won't happen! Always examine your ground plane pair at the end of the routing process to make sure you haven't cut any big slots in it with string of vias. Finally, _real_ engineers use DRAMs! ;-) HTH., Syms. p.s. Did I make it clear that the ground is important?
From: TSMGrizzly on 4 Feb 2010 05:57 On Feb 4, 7:28 pm, Symon <symon_bre...(a)hotmail.com> wrote: > On 2/4/2010 8:23 AM, David Brown wrote: > > > > > > > You have a lot more experience at this sort of thing than me, Rick, so > > I'm a little wary of disagreeing with you. But I'm sure you'll tell me > > if I get something wrong! > > > I don't see that you have to worry about any termination here. With fast > > enough signal edges, you can get ringing - but that typically will not > > matter because you don't sample the signals until the ringing has > > subsided. > > > Ringing can cause a few problems - the overshoot/undershoot can go > > outside the voltage range of the pins on the line, it can cause > > interference for neighbouring signals, you can't read the signal while > > it is ringing, and it can cause big trouble when connected to > > edge-sensitive inputs. But most of these are not going to be a problem > > in your case, I think. > > Dear David, Steve, > > Going "outside the voltage range of the pins on the line" can break the > device. IIRC there are Xilinx appnotes which go into this problem in > some detail; powering 3.3V with 3V was something I think they suggested! > (See XAPP653) > Also, the thing will probably fail any sort on electromagnetic > compliance test that you would need to do before you sell this. And you > are unlikely to be able to listen to 'The Archers' while this thing is > in the room. > > To the OP, in the absence of micro-vias, I would recommend a 6 layer > board. Maybe like this:- > > signal > signal > ground > ground > power/signal > signal > > Keep all the layers as close together as your PCB manufacturer allows > and make up the board thickness with the core between the two ground > layers. Xilinx on the top. Route the powers, or use copper pours. Try to > make room for bypass caps on the back of the board from the FPGA. This > stack up will make it very difficult for a beginner to go wrong from an > SI point of view, as ground is always near. This is particularly true if > you have a nice spread of ground vias tying the two ground planes > together. That doesn't mean you shouldn't simulate it with Hyperlynx, > but I bet that won't happen! Always examine your ground plane pair at > the end of the routing process to make sure you haven't cut any big > slots in it with string of vias. > > Finally, _real_ engineers use DRAMs! ;-) > > HTH., Syms. > > p.s. Did I make it clear that the ground is important? Thanks all, for the good information! This will definitely help. Uwe, I'll take a look at your script, that seems like it could be very handy! Symon, DRAM is out of the question in this design, gotta stick with SRAM.. and it isn't really for sale, it's a custom one-off thing so I don't think I have to worry about compliance tests. I was hoping to keep the cost down a little by skimping on the layers but I'm sure I can afford to go with six layers just fine.. six is what I initially told the boss would probably be happening, I was just wondering if I could get away with four. Steve
From: RCIngham on 4 Feb 2010 06:08 >Thanks for the input so far, guys! > >I will have two SRAM chips and one parallel EEPROM in one memory >space, and one additional RAM chip in a separate memory space so I >know for sure that that one gets its own dedicated address/control/ >data lines. >I was just wondering if the signal integrity would be hurt by extra >loading in chaining up the ones that are on the same bus, but I had a >hunch that at these speeds it wouldn't be such a big problem. > I suggest checking the data bus turn-off (->Z) time of the EEPROM. It might be rather long, meaning that an EEPROM read followed by an SRAM access causes data corruption. If it is too long, either put an extra buffer with fast turn-off on the board, or else use dedicated data signals and mux it in the FPGA. --------------------------------------- Posted through http://www.FPGARelated.com
From: John Adair on 4 Feb 2010 08:38 Steve I'll start by pointing you at Raggedstone1 http://www.enterpoint.co.uk/moelbryn/raggedstone1.html as an example of what can be done in 4 layers with a 456 pin BGA. At speeds of 10-25Mhz I generally just about count that as DC and don't really do anything other that what we do normally and that is hand route. Handrouting, using your brain, gives much better results - less vias, shorter tracks and so on and contributes a lot to a good result. Frightening as might seem even our Merrick1 product with about circa 18,000 routes is done that way. If you can get away with just the outer 2 rows of ball you should be able to use a "slack" technology of maybe 6mil/0.150mm track and gap and that will save you money at manufacture. On power split planes is a good technique if used very carefully but using polygon fills on tracking layers will also help. On the Raggedstone1 mentioned above there are something like 7 different power rails under BGA and that was one the major difficulties with that design so it's all possible. Later FPGA families do help by reducing the need for so many rails. On buses versus individual interfaces I would do buses at 25MHz. At 100MHz+ I would go the other way usually. John Adair Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. On 4 Feb, 05:22, TSMGrizzly <sbatt...(a)yahoo.co.jp> wrote: > Hi guys.. I'm getting ready to start working on my first board layout > with a BGA package (FG456). First will be a prototype for sure. > I was just wondering a few things... > > Probably the critical part of my design will be interface to a few > asynchronous SRAMs. > > In a relatively low speed design (buses at 10-25MHz) do I need to > worry about things like termination and trace length on the RAM buses? > Should I dedicate address/data pins to each chip in a shared memory > space, or is it better to daisy chain them on a bus? (It seems to me > that routing will be a little easier if each chip gets its own > lines..) > > If I won't be using the innermost IO pins, can I get away with a 4- > layer design, two signal layers and power/ground? > > Looking at a Xilinx app note with a suggested escape route for this > package, they have three signal layers with 5 mil width traces, the > third of which I believe I can do without... > And lastly, I guess that I will be needing 1.8 and 2.5V supplies, as > well as 3.3V for all of my I/O supplies.. should these all be routed > in the dedicated power layer? If the layer is mostly covered a plane, > which voltage is supposed to be the plane? 3.3V? > > And lastly, when connecting I/Os, is there any sensible approach? My > tendency is to want to choose the I/Os so that everything lines up > nicely, but I find it to be a hassle in this case, that in Eagle we > have to connect nets in the schematic first and can't back-annotate > from the board. > > Anything else I should be worrying about? > > Cheers, > > Steve
From: Nial Stewart on 4 Feb 2010 08:41
> Try to make room for bypass caps on the back of the board from the FPGA. You can use 0402 resistors with 0.6mm round pads on 1mm centres. This allows thm to be placed on the back of the BGA 'matching' the BGA pads, and allows almost one cap per power & gnd pair. Check with your assembly house that they're happy with this, mine does it no problem (they built a couple of boards with 0.5mm pads before telling me to make them bigger). Nial |