Board layout for FPGA
in [FPGA]
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From: rickman on 6 Feb 2010 03:13 On Feb 5, 9:24 pm, glen herrmannsfeldt <g...(a)ugcs.caltech.edu> wrote: > Symon <symon_bre...(a)hotmail.com> wrote: > > On 2/5/2010 9:53 PM, glen herrmannsfeldt wrote: > >> Yes. Actually, I believe that for the really highest frequency > >> components, that they are supplied by the plane itself. (Especially > >> as signals won't be switching at exactly the same time.) > > If these highest frequencies are supplied by the planes, why do Xilinx > > and Altera put capacitors on the BGA substrate? That must cost money. > > Are they wrong? > > OK, not quite the highest frequencies, but almost. > > The highest that get through the inductance of the package and > past the internal capacitors. > > I think it isn't so hard to calculate the impedance of an > infinite plane with a hole (via) as a function of frequency. > That should partly answer the question. Two different problems. The capacitance of the power and ground planes closely spaced is effective at frequencies well above that where capacitors become highly inductive and the impedance rises to a point of being useless. So any caps used inside the package are not there to handle "the highest frequencies". To be honest, I don't know why they would put caps inside the package unless their packages are poorly designed, unless it is to account for poor designers... In a discussion some time back between an engineer and a Xilinx rep about the "recommended" decoupling caps, it was admitted that their recommendation was overkill for most designs since there is such a wide range of designs implemented in their parts. Reading between the lines I would say this means they were recommending overkill for the designers who can't figure it out for themselves. When was the last time a design review said you had too many decoupling caps? I firmly believe what Lee Ritchey showed me (that only a fraction of the number of caps normally used are really needed) but I still try to use one per power pin! Call it superstition or just lack of confidence in myself. But no one's design failed because he used too many caps on the power plane. BTW, Lee Ritchey's book, "Right the First Time..." is available on CD for $25. I recommend it. Everything I have said here is from what I learned in his course using that book. Rick
From: whygee on 6 Feb 2010 03:42 Hi Rick ! rickman wrote: > Lee Ritchey showed me (that only a fraction of the number > of caps normally used are really needed) but I still try to use one > per power pin! Call it superstition or just lack of confidence in > myself. But no one's design failed because he used too many caps on > the power plane. Excellent point, I feel concerned by this remark :-) > Rick yg -- http://ygdes.com / http://yasep.org
From: Symon on 6 Feb 2010 08:01 On 2/6/2010 8:13 AM, rickman wrote: > To be honest, I don't know > why they would put caps inside the package > > Rick The caps are on the package because the inductance of the connecting vias and package balls means that, no matter how good the bypassing is on the PCB, the die on the package will have bypassing problems with it's supply. This is why I believe the high Q bypassing from a power plane and a ground plane doesn't help, and the layers can be arranged differently to achieve better results by optimising other areas. Syms.
From: rickman on 6 Feb 2010 12:38 On Feb 6, 8:01 am, Symon <symon_bre...(a)hotmail.com> wrote: > On 2/6/2010 8:13 AM, rickman wrote: > > > To be honest, I don't know > > why they would put caps inside the package > > > Rick > > The caps are on the package because the inductance of the connecting > vias and package balls means that, no matter how good the bypassing is > on the PCB, the die on the package will have bypassing problems with > it's supply. This is why I believe the high Q bypassing from a power > plane and a ground plane doesn't help, and the layers can be arranged > differently to achieve better results by optimising other areas. I understand what you are saying, but it does not address the problem that the capacitors you say are used inside the chip package no longer decouple effectively above 100 MHz or so. Certainly the noise transients from signal switching in an FPGA extend well above 100 MHz. If the inductance of the package leads do not allow effective connection to power/ground planes, the part will always have noise problems. One of the ways around the inductance of the package leads is to use more than one lead. I believe many packages have as many as 40 or more ground leads. So the effective impedance is then 40 times lower than what is calculated for one pin. Has that been considered in your analysis? Just as decoupling caps can be effective well above their self resonant frequency where they are effectively inductors (because the power delivery system impedance is still very low with many in parallel), the inductors we call power pins can still be an effective power conduit as long as the total impedance is low enough. I keep asking you if you have done any real analysis or measurements of what you are stating? I am no guru, but I was *very* impressed by what Lee Ritchey said just because he has full support for just about everything he stated in his course (except maybe that the food was good at the Chinese restaurant). Rick
From: glen herrmannsfeldt on 6 Feb 2010 14:01
In comp.arch.fpga rickman <gnuarm(a)gmail.com> wrote: (snip) > My bad here. I am the one saying that the planes will capacitively > couple and allow the return current to cross slots in one plane by > jumping to the other. I got your post mixed up with Symon's post > where he recommends multiple ground planes stitched together with vias > rather than capacitively coupled power/ground planes. Well, you want it to stay low impedance all the way down to DC. >> (snip, I wrote) >> I completely agree. ?Well, actually computers are probably about >> fast enough to do the whole calculation for at least one board trace >> using the actual geometry. ?With linearity you can compute each one >> and add them together. ? >> > Lee has done that. ?One test he made >> > that really impressed me was to show that a decoupling cap does not >> > need to be close to a pin to work well. ?If the power and ground plane >> > are closely spaced, the impedance is very low. ?If you understand >> > transmission lines, you will know that the current into (or out of) a >> > driver into the transmission line is constant until the signal reaches >> > the other end and depending on what load it finds, either continues >> > until the reflection returns to the driver (as in a series terminated >> > line with high impedance load) or keeps flowing as when it reaches the >> > decoupling cap. ? >> Well, it has the impedance of the transmission line itself. >> That depends on the inductance and capacitance of the conductors >> making up the transmission line. ?You can consider a linear >> transmission line as a sequence of series inductors and parallel >> capacitors of constant value per unit length. ?Consider the >> impedance of a finite length open ended transmission line as >> a function of frequency. ?For some frequencies the impedance will >> be very low, for others it will be very high. ?This property >> is used for impedance matching and filtering in RF circuits. > I am aware of what a transmission line is. That is my point. The > transmission line of closely spaced planes is a very low impedance > which supplies current for the full time it takes the impulse to reach > the cap. So the spacing of the caps is not at all critical contrary > to what many will tell you. I believe, though, that radial transmission lines aren't discussed much in classes. I hadn't thought of them much until I was replying to your post. A google search for them brought up the paper that I tried to reference. I did the search on a different computer and copied the link by hand. I will try again. (Interesting all the ads that come for towing companies and transmission repair.) (snip) >> Now, consider the case of a signal going into or out of a supply >> plane. ?Now instead of the constant inductance and capacitance >> per unit length you have concentric rings. ?The inductance decreases >> and the capacitance increase with radial distance. ?In transmission >> line terms, it is a line with the impedance decreasing with R. >> Impedance decreases pretty fast, too. ? >> A quick web search finds a paper that looks interesting on just >> this problem. ? >> http://www.waves.utoronto.ca/prof/gleefth/Backup_Old/jpub/6.pdf >> The paper has much more detail than even I know, and includes >> comparisons of calculations and actual boards. > What paper? I get a 404 error, page not found. Still, I don't see > the problem you seem to be describing. So the impedance drops with > increasing distance, low impedance in the power supply is a good > thing, no? Why would it dropping be a bad thing? OK, try again. http://www.waves.utoronto.ca/prof/gelefth/Backup_Old/jpub/6.pdf he seems to even include the reflections of other vias, which seems more than is needed to me, but... It looks like the other papers on on slot antenna design, so he is considering PC board design in slot antenna terms. > Lee actually has impedance vs. frequency measurements of power/ground > planes and it is pretty interesting. They don't do much below 100 MHz > or so, but beyond that the impedance is an up/down trace (all > adequately low) until it finally starts to climb above several GHz. > IIRC he explained the the sawtooth as having to do with the board > dimensions. I guess it has something to do with standing waves, but > it was some four years ago and I don't recall for sure. With some bad luck you might get a resonance (standing wave) where the impedance didn't stay low. > I do remember that he showed some interesting interactions between the > plane capacitance and the inductance of the small sized and valued > decoupling caps. They have a resonance around 100-200 MHz I think, > which drives the impedance way up at that value. His solution was to > add other value caps which effectively move that resonance and also > damp it out to where it is acceptable. I think he showed a board > where he used a total of three different values of ceramic caps, but > only a small number of each, to get a very quiet board with a very > constant power delivery system impedance. When I took the course, I > understood how to figure it all out, but I have not had a design with > difficult power decoupling needs, so I have forgotten some of it. > Good thing I still have the book... somewhere... In the old days, it might be that the tolerance kept the resonances from being too close. The uniformity is so good now that they will all have resonance too close together. (snip) > So the physics of each board is different??? The board Lee > constructed was a test board. I don't recall what he used for a > source of the transient, but he had spots for capacitors at a minimum > of three distances connected to the power/ground planes with optimally > short runs to the vias. He populated the caps one at a time and > measured the effectiveness finding that it dropped off barely at all > at an inch, IIRC and only moderately at a couple or three inches. The > point is that it is not really needed to put the cap right on top of > the power pin. A good power/ground plane pair is much more > important. (snip) > My point is that this is all theory. Unless you take some > measurements to verify what you are saying, you can't say it is an > accurate description of a real board and chip. Also consider that one > via is not a power supply. Vias are used in parallel giving an > effectively low impedance. Hopefully the link is right now. He does both theory and measurement. -- glen |