Board layout for FPGA
in [FPGA]
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From: glen herrmannsfeldt on 6 Feb 2010 14:04 Symon <symon_brewer(a)hotmail.com> wrote: > On 2/6/2010 8:13 AM, rickman wrote: >> To be honest, I don't know >> why they would put caps inside the package > The caps are on the package because the inductance of the connecting > vias and package balls means that, no matter how good the bypassing is > on the PCB, the die on the package will have bypassing problems with > it's supply. This is why I believe the high Q bypassing from a power > plane and a ground plane doesn't help, and the layers can be arranged > differently to achieve better results by optimising other areas. I think what he means is that the resonance will still be too low even inside the package. -- glen
From: Symon on 6 Feb 2010 19:25 On 2/6/2010 7:04 PM, glen herrmannsfeldt wrote: > Symon<symon_brewer(a)hotmail.com> wrote: >> On 2/6/2010 8:13 AM, rickman wrote: >>> To be honest, I don't know >>> why they would put caps inside the package > >> The caps are on the package because the inductance of the connecting >> vias and package balls means that, no matter how good the bypassing is >> on the PCB, the die on the package will have bypassing problems with >> it's supply. This is why I believe the high Q bypassing from a power >> plane and a ground plane doesn't help, and the layers can be arranged >> differently to achieve better results by optimising other areas. > > I think what he means is that the resonance will still be too > low even inside the package. > > -- glen What resonance?
From: Symon on 6 Feb 2010 19:37 On 2/6/2010 5:38 PM, rickman wrote: > > I keep asking you if you have done any real analysis or measurements > of what you are stating? > Well, this was the first time you asked IIRC, but thank you for doing so. The answer is "For sure". I've used Hyperlynx and Spice on my boards. I guess you have also, or else you would not be able to post your opinions without worrying you might giving someone a bum steer. > I am no guru, Really? > > but I was *very* impressed by > what Lee Ritchey said just because he has full support for just about > everything he stated in his course (except maybe that the food was > good at the Chinese restaurant). > > Rick You seem to be _very_ impressed. Almost as impressed as Steve Wier. http://www.freelists.org/post/si-list/Lee-Ritcheys-book,4
From: Symon on 6 Feb 2010 19:44 On 2/6/2010 6:15 PM, rickman wrote: >> will increase with frequency. > > My point is that this is all theory. Unless you take some > measurements to verify what you are saying, you can't say it is an > accurate description of a real board and chip. Also consider that one > via is not a power supply. Vias are used in parallel giving an > effectively low impedance. > > Rick Rick, Do you measure every resistor you put on a board. Ohm's law is a theory, after all. Syms xx
From: glen herrmannsfeldt on 6 Feb 2010 20:03
Symon <symon_brewer(a)hotmail.com> wrote: (snip on bypass capacitors) > What resonance? The limit to the useful frequency range of a capacitor is when it reaches resonance with the series (lead, package, etc.) inductance. Graph impedance vs. frequency, when the reactive component crosses zero that it resonance. -- glen |