Board layout for FPGA
in [FPGA]
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From: Symon on 5 Feb 2010 08:45 On 2/5/2010 11:48 AM, Martin Thompson wrote: > rickman<gnuarm(a)gmail.com> writes: > >> BTW, you are aware that the power plane is just as effective as the >> ground plane for determining the impedance. > > Yes, but the OP needs to be aware that care can be required when > switching your signal trace from one layer to another. When you switch > to a layer which references the other supply rail, then the return > current has to also switch layers. If the way it has to do that is > via a decoupling cap a long way away then the current loop can be > quite large. > > I got Henry Ott's new book just this morning, and he has some > discussion on p630... If you use Amazon's "search in this book" > feature from here: > > http://www.amazon.co.uk/Electromagnetic-Compatibility-Engineering-Henry-Ott/dp/0470189304/ > > and search for "Changing Reference Planes", you can see pp 630-631. > > To the OP - ...and then buy it :) > > Cheers, > Martin > Hi Martin, It would appear Mr. Ott agrees that multiple ground planes with a big centre core are a good idea, even on a four layer board. Fig. 16-15. He must be a smart guy!! ;-) Also, Fig. 16-16 he specifically says that signal signal ground power signal signal is _not_ recommended. Looks like he would do signal ground signal signal ground signal with a thick centre core and routed powers. This way the internal signal layers are shielded. I tend to agree. The ssggss stack I suggested because I almost always use laser drilled micro-vias on my boards, so I need two signal layers on the outside. Also, my enclosures do the EMC shielding. With standard vias, sgssgs is probably better. Cheers, Syms.
From: rickman on 5 Feb 2010 09:55 On Feb 5, 5:15 am, "Nial Stewart" <nial*REMOVE_TH...(a)nialstewartdevelopments.co.uk> wrote: > > John, > > I don't think I can get away with only the outer two rows of balls, > > I'll probably need the two inside of that as well-- I was thinking of > > breaking out the outer two on one signal layer and the inner two in > > another, as suggested in the Xilinx app note I saw. It was a tight > > squeeze but they wrote .127mm traces, and .3/.6mm on the vias, which > > is the standard offering of the board house we're using.. it's > > possible to ask for smaller, for an extra chunk of change. > > With 1mm ball pitch I use 0.5mm pads, 0.5mm vias with 0.25mm drills. > > This is pretty much run of the mill for fab houses and shouldn't > add much to costs. 0.25 mm drill is 10 mil. I have had fab houses say they can't do 10 mil. One in particular applied a "standard" rule of +- 3 mil tolerance and used a 13 mil drill without telling me. Of course, without saying any names, I don't use Sunstone anymore. ;^) (They also had a >20% Xout rate on that run and had to do a second run to get me the last panel, not that I would ever bad mouth them...) The lower limit for the lower end board houses (in terms of costs not quality) tends to be around 15 mil. I don't think you can do any of these BGAs using 15 mil vias, so the truly low end houses are likely out anyway. It is important to choose a *good* fab house. I have found quality to vary a *lot*. Rick
From: Nial Stewart on 5 Feb 2010 10:58 > The lower limit for the lower end board houses (in terms of costs not > quality) tends to be around 15 mil. I don't think you can do any of > these BGAs using 15 mil vias, so the truly low end houses are likely > out anyway. It is important to choose a *good* fab house. I have > found quality to vary a *lot*. Aye, I'd assumed a 'proper' board house, not a pile em high outfit like PCB pool etc (although I've always had good results using pcb pool for lower tech boards). Nial.
From: rickman on 5 Feb 2010 11:08 On Feb 5, 8:45 am, Symon <symon_bre...(a)hotmail.com> wrote: > On 2/5/2010 11:48 AM, Martin Thompson wrote: > > > rickman<gnu...(a)gmail.com> writes: > > >> BTW, you are aware that the power plane is just as effective as the > >> ground plane for determining the impedance. > > > Yes, but the OP needs to be aware that care can be required when > > switching your signal trace from one layer to another. When you switch > > to a layer which references the other supply rail, then the return > > current has to also switch layers. If the way it has to do that is > > via a decoupling cap a long way away then the current loop can be > > quite large. > > > I got Henry Ott's new book just this morning, and he has some > > discussion on p630... If you use Amazon's "search in this book" > > feature from here: > > >http://www.amazon.co.uk/Electromagnetic-Compatibility-Engineering-Hen... > > > and search for "Changing Reference Planes", you can see pp 630-631. > > > To the OP - ...and then buy it :) > > > Cheers, > > Martin > > Hi Martin, > > It would appear Mr. Ott agrees that multiple ground planes with a big > centre core are a good idea, even on a four layer board. Fig. 16-15. He > must be a smart guy!! ;-) > > Also, Fig. 16-16 he specifically says that > > signal > signal > ground > power > signal > signal > > is _not_ recommended. > > Looks like he would do > > signal > ground > signal > signal > ground > signal > > with a thick centre core and routed powers. This way the internal signal > layers are shielded. I tend to agree. The ssggss stack I suggested > because I almost always use laser drilled micro-vias on my boards, so I > need two signal layers on the outside. Also, my enclosures do the EMC > shielding. With standard vias, sgssgs is probably better. > > Cheers, Syms. In reply to both of your posts, I will say that there is a *lot* of misinformation out there. There is *NO* one way to stack up PCBs. I once took a class in "High Speed Digital Design" with Lee Ritchey. Some "experts" in the field will explain the theory behind what they say. Lee Ritchey not only gives the theory, he also shows detail simulations and even builds test boards to verify that what he is saying is how it works in the real world. That impressed me greatly. As to the return current having to "jump" between layers being a problem, if you use the ssgpss stackup and have the power and ground very close rather than widely spaced, the capacitive coupling allows the signal to switch between them without issue. In fact, when splitting a plane for multiple power sections, the return current will switch from one power plane, to the ground plane and back to the next power plane as if they were all one plane. This is because of the capacitive coupling between layers. Of course this only works for the highest frequency components of the signals, but that's all we really care about, no? -------+ +-------> Return Current =======| |======== Power Planes | | +--+ =================== Ground Plane The ascii art may not come out too well depending on your browser or newreader, but I hope you get the idea. I couldn't view the pages in Ott's book so I can't respond to that. The one point I most learned from Lee Ritchey's course is that you should never take any expert's opinion as fact. Many experts make mistakes and a number of things look good on paper while the real world works differently. Only trust an expert opinion if it is backed up by reliable proof. How does Ott "prove" his analysis, or is it just a paper analysis? Rick
From: Mike Harrison on 5 Feb 2010 14:15
>Yes, one common element is that most designs apply overkill in the >supply decoupling area. When an engineer uses a method and it works, >it is like the elephant protection charm... you don't see any >elephants do you, so it must be working! Just for amusement, I tried an experiment on a simple FPGA board I designed recently -board has a Lattice EC3, driving a small TFT LCD from video data in NAND flash. It's a 2 layer PCB, with about ten 100n decouplers wherever space allowed and a couple of 1u ceramics on each rail. I removed ALL the decouplers apart from a single 1u on each rail to keep the LDOs happy. Board still worked just fine..... didn't do any noise measurements though.... A few years ago I saw a very amusing talk at London Dorkbot - in an attempt to bring old board games up to date, James Larson created "Motherboard Operation" - players take it in turns to snip components from a working, running PC motherboard until it stops working... This was accompanied by "PC PSU Buckaroo" - players choose and add more and more loads to an old PC power supply until it fails.... |