Debouncing....at About 1Mhz - Uobtanium Obtained ;-)
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From: Jim Thompson on 10 Nov 2007 20:03 On Sat, 10 Nov 2007 16:19:54 -0800, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Sat, 10 Nov 2007 17:15:41 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > >>On Sat, 10 Nov 2007 15:02:17 -0800, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson >>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>> >>>>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin >>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> >>>>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >>>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>>> >>>>[snip] >>>>>> >>>>>>Now please present us with your "solution" with component names and >>>>>>values and I'll simulate it side-by-side with my design. >>>>> >>>>> >>>>>I rarely simulate. Design is the reverse of simulation. Design forces >>>>>the desired results, so why simulate? >>>>> >>>>[snip] >>>> >>>>So you've been converted to the Bob Pease school of hand waving ?:-) >>>> >>>>My POV: Design puts the idea onto paper. Simulation proves that what >>>>is on the paper really works. But simulators don't "design". In my >>>>business, simulation "proof" is required for each and every process >>>>corner, otherwise the customer doesn't "buy". >>>> >>>> ...Jim Thompson >>> >>> >>>Your Sysreset sets Q high, but your sim starts with Q low. Why? >>> >>>John >>> >> >>The default set-ups included FF initial conditions Q=0. If I uncheck >>that box it starts, as would be expected, with Q=1. >> >> ...Jim Thompson > >Well, run that. It's more interesting. > >John Yep. It takes one cycle for the output to be correct. ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | America: Land of the Free, Because of the Brave
From: John Larkin on 10 Nov 2007 20:44 On Sat, 10 Nov 2007 18:03:07 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >On Sat, 10 Nov 2007 16:19:54 -0800, John Larkin ><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>On Sat, 10 Nov 2007 17:15:41 -0700, Jim Thompson >><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >> >>>On Sat, 10 Nov 2007 15:02:17 -0800, John Larkin >>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>> >>>>On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson >>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>> >>>>>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin >>>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>>> >>>>>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >>>>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>>>> >>>>>[snip] >>>>>>> >>>>>>>Now please present us with your "solution" with component names and >>>>>>>values and I'll simulate it side-by-side with my design. >>>>>> >>>>>> >>>>>>I rarely simulate. Design is the reverse of simulation. Design forces >>>>>>the desired results, so why simulate? >>>>>> >>>>>[snip] >>>>> >>>>>So you've been converted to the Bob Pease school of hand waving ?:-) >>>>> >>>>>My POV: Design puts the idea onto paper. Simulation proves that what >>>>>is on the paper really works. But simulators don't "design". In my >>>>>business, simulation "proof" is required for each and every process >>>>>corner, otherwise the customer doesn't "buy". >>>>> >>>>> ...Jim Thompson >>>> >>>> >>>>Your Sysreset sets Q high, but your sim starts with Q low. Why? >>>> >>>>John >>>> >>> >>>The default set-ups included FF initial conditions Q=0. If I uncheck >>>that box it starts, as would be expected, with Q=1. >>> >>> ...Jim Thompson >> >>Well, run that. It's more interesting. >> >>John > >Yep. It takes one cycle for the output to be correct. > > ...Jim Thompson It seems to work, but it's awfully convoluted. It would be, for me, like one of those things that I designed but that I can barely understand myself; there are too many possible states, and the dflop clock sometimes comes from the input, and sometimes comes from the input xored with the internal delay. And the input can chatter, or it could be a single edge of either polarity. All those conditions have to be proven to work, and proving it is too much work. I avoid clever stuff like that, in hardware and in software. Sorry, but I prefer my first circuit, because it's a lot easier to understand. John
From: John Fields on 10 Nov 2007 20:55 On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin ><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >> >[snip] >>> >>>Now please present us with your "solution" with component names and >>>values and I'll simulate it side-by-side with my design. >> >> >>I rarely simulate. Design is the reverse of simulation. Design forces >>the desired results, so why simulate? >> >[snip] > >So you've been converted to the Bob Pease school of hand waving ?:-) > >My POV: Design puts the idea onto paper. Simulation proves that what >is on the paper really works. But simulators don't "design". In my >business, simulation "proof" is required for each and every process >corner, otherwise the customer doesn't "buy". --- I used to be in Larkin's corner, defending "build and test" over "simulate", but after writing a few simulators to solve specific problems posed here on sed, which couldn't be solved, practically, any other way, I decided to lay down my wire-wrap gun until the machine worked in the computer. Then, along came wonderful, free LTSPICE. I've designed stuff using it which I never had to physically build, but which worked and which I got paid for, which is a joy. A feeling I'm sure you enjoyed before I did. :-) -- JF
From: D from BC on 10 Nov 2007 22:07 On Sat, 10 Nov 2007 19:55:00 -0600, John Fields <jfields(a)austininstruments.com> wrote: >On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > >>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>> >>[snip] >>>> >>>>Now please present us with your "solution" with component names and >>>>values and I'll simulate it side-by-side with my design. >>> >>> >>>I rarely simulate. Design is the reverse of simulation. Design forces >>>the desired results, so why simulate? >>> >>[snip] >> >>So you've been converted to the Bob Pease school of hand waving ?:-) >> >>My POV: Design puts the idea onto paper. Simulation proves that what >>is on the paper really works. But simulators don't "design". In my >>business, simulation "proof" is required for each and every process >>corner, otherwise the customer doesn't "buy". > >--- >I used to be in Larkin's corner, defending "build and test" over >"simulate", but after writing a few simulators to solve specific >problems posed here on sed, which couldn't be solved, practically, >any other way, I decided to lay down my wire-wrap gun until the >machine worked in the computer. > >Then, along came wonderful, free LTSPICE. > >I've designed stuff using it which I never had to physically build, >but which worked and which I got paid for, which is a joy. > >A feeling I'm sure you enjoyed before I did. :-) I still find it amazing that after benchtesting, I can see that I forgot to include parasitics in a circuit model. After including the parasitics in the model, I get the sim waveforms that I see on the scope :) Bouncing between model and bench and model and bench can build a good model. D from BC
From: John Fields on 10 Nov 2007 22:26
On Sat, 10 Nov 2007 19:07:16 -0800, D from BC <myrealaddress(a)comic.com> wrote: >On Sat, 10 Nov 2007 19:55:00 -0600, John Fields ><jfields(a)austininstruments.com> wrote: > >>On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson >><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >> >>>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin >>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>> >>>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>> >>>[snip] >>>>> >>>>>Now please present us with your "solution" with component names and >>>>>values and I'll simulate it side-by-side with my design. >>>> >>>> >>>>I rarely simulate. Design is the reverse of simulation. Design forces >>>>the desired results, so why simulate? >>>> >>>[snip] >>> >>>So you've been converted to the Bob Pease school of hand waving ?:-) >>> >>>My POV: Design puts the idea onto paper. Simulation proves that what >>>is on the paper really works. But simulators don't "design". In my >>>business, simulation "proof" is required for each and every process >>>corner, otherwise the customer doesn't "buy". >> >>--- >>I used to be in Larkin's corner, defending "build and test" over >>"simulate", but after writing a few simulators to solve specific >>problems posed here on sed, which couldn't be solved, practically, >>any other way, I decided to lay down my wire-wrap gun until the >>machine worked in the computer. >> >>Then, along came wonderful, free LTSPICE. >> >>I've designed stuff using it which I never had to physically build, >>but which worked and which I got paid for, which is a joy. >> >>A feeling I'm sure you enjoyed before I did. :-) > >I still find it amazing that after benchtesting, I can see that I >forgot to include parasitics in a circuit model. >After including the parasitics in the model, I get the sim waveforms >that I see on the scope :) > >Bouncing between model and bench and model and bench can build a good >model. --- And a good, well characterized product as well, yes? -- JF |