Debouncing....at About 1Mhz - Uobtanium Obtained ;-)
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From: John Larkin on 11 Nov 2007 19:21 On Sun, 11 Nov 2007 14:46:32 -0800, D from BC <myrealaddress(a)comic.com> wrote: >On Sun, 11 Nov 2007 14:20:54 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > >>On Sun, 11 Nov 2007 13:07:10 -0800, D from BC >><myrealaddress(a)comic.com> wrote: >> >>>On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin >>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>> >>[snip] >>>> >>>>I was also thinking that the origical hysteresis idea was OK except >>>>that the hyst band of cmos schmitts is poorly defined. That's fixable >>>>by defining it better, namely by adding additional hysteresis. The >>>>numbers ought to work. >>>> >>>>John >>>> >>> >>>Damn...that's right...This is freakn scope trigger tech... :P >>>I didn't notice. >>>Bummer... :( I'm reinventing the wheel again. >>> >>>Now I'm wondering if I could have cheated and looked up oscilloscope >>>trigger circuit patents to dodge a whole lot of dinking with gates, D >>>ff's and one shots. >>>There should be ooodles of trigger art since the invention of the >>>oscilloscope. >> >>Well, DUH! My circuit trips on the first edge and ignores all others >>"until sweep is complete"... it's called BLANKING ;-) >> >>> >>>What to do..... >>>Use time sifting through mountains of patents >>>versus >>>use time designing from scratch.. >>> >>> >>>D from BC >> >> ...Jim Thompson > >lol... When I first posted this problem (Debouncing....at About 1Mhz). >I did suspect it was a classic problem with a known classic solution. >I just didn't think of in what... Oscilloscopes! Doh! :( > >About all schematics... > >The thing I don't like about the use of comparator solutions is a >bucketload of resistors are needed as seen in my design and JF's >design. > >The JL based 2 D ff + one shot I posted has a lower parts count and >the same goes for your (Jim) recently posted schematics. >All with only 1 Dff prop delay off the primary pos edge and primary >neg edge. > >It looks like it's down to D flip flops vs comparators. > >I like the parts count of Dff based designs and I'm going to look at'm >closer.. > > >D from BC My first post, the quad xor + dff + rc, still looks like the simplest and fastest circuit so far. It appears to be hazard free, too, at least using cmos transmission-gate flipflops. The last one I posted, 1 xor and 1 dflop and 1 rc, is sort of a hybrid of my circuit and Jim's. It's not bad either. Too bad the really fast tiny-logic flops don't generally have qbar. John
From: John Larkin on 11 Nov 2007 19:32 On Sun, 11 Nov 2007 14:16:50 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >On Sun, 11 Nov 2007 11:34:35 -0800, John Larkin ><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>On Sun, 11 Nov 2007 08:25:59 -0700, Jim Thompson >><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >> >> >>> >>>Think of the XOR as a device that is switched from being an inverter >>>to being a buffer. The switching does not occur while clock (input) >>>edges are present. >>> >>>>And the input can chatter, or it >>> >>>Does nothing after the first transition... it's an edge-triggered >>>flop. >>> >>>>could be a single edge of either polarity. All those conditions have >>>>to be proven to work, and proving it is too much work. >>>> >>>>I avoid clever stuff like that, in hardware and in software. Sorry, >>>>but I prefer my first circuit, because it's a lot easier to >>>>understand. >>>> >>>>John >>> >>>When I feel confused I drinks a glass of wine ;-) >>> >>> ...Jim Thompson >> >>Coffee works better for me. >> >>OK, how about this? >> >>http://img225.imageshack.us/my.php?image=catchernv0.jpg >> >> >>John > >I found, at least with 74HC' stuff, that I needed to delay the clock >flip-over as well... looked like SUAH timing was violated. > > ...Jim Thompson This one looks OK to me. The rc keeps D from changing anywhere near clock edges. The reason the clock goes back low is because qbar has already flipped, and you can't take that back. This makes a short (2 pd) positive clock blip every input transition, or a whole mess of them when the input chatters. All of them clock the "old" rc filtered level into the flop. It's close to my original circuit, but uses your xor thing to eliminate the three dummy delay stages. This is close to minimal from a parts count standpoint. 4 parts approaches 0 parts as design time approaches infinity. John
From: D from BC on 11 Nov 2007 19:40 On Sun, 11 Nov 2007 18:03:13 -0600, John Fields <jfields(a)austininstruments.com> wrote: >On Sun, 11 Nov 2007 13:00:31 -0800, John Larkin ><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>On Sun, 11 Nov 2007 12:26:01 -0600, John Fields >><jfields(a)austininstruments.com> wrote: >> >>>On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin >>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>> >>>>On Sun, 11 Nov 2007 01:32:07 -0800, D from BC >>>><myrealaddress(a)comic.com> wrote: >>> >>>>>Check out my hysteretic hairball! :O * >>>>>http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg >>>>>569Kb >>>> >>>>Yeah, I was thinking along those lines. This is a "feed-beside" sort >>>>of concept, a brutally fast forward path, with slower tweaks off to >>>>the side to fix the low-speed defects. This was the concept Tek used >>>>in their 7000 series oscilloscopes. >>>> >>>>I was also thinking that the origical hysteresis idea was OK except >>>>that the hyst band of cmos schmitts is poorly defined. That's fixable >>>>by defining it better, namely by adding additional hysteresis. The >>>>numbers ought to work. >>> >>>--- >>>I think this pretty much takes care of it all. >> >> >>Looks pretty good. The only hazard I can see is that a very fast spike >>can blow through the first comparator before the second one has time >>to come back around. That's a hazard with most all comparators that >>have external hysteresis. > >--- >These have internal hysteresis but, after just a cursory glance, I >haven't figured out how to make that work in this application. >--- > >>That's only a problem if the input can in fact have such fast spikes, >>which in this case maybe it can't. > >--- >But maybe it can.. > >I've asked the OP >to disclose what the input signal looks like, so maybe we'll be >graced with an answer soon. There won't be any razor thin spikes.. I believe your circuit will work just fine. The bug I have with comparator solutions is the bucketload of resistors needed. I hate smd layout :) So Jim's Dff designs look good. D from BC
From: D from BC on 11 Nov 2007 19:50 On Sun, 11 Nov 2007 15:36:37 -0800, JosephKK <joseph_barrett(a)sbcglobal.net> wrote: >D from BC myrealaddress(a)comic.com posted to sci.electronics.design: > >> On Sat, 10 Nov 2007 19:35:26 -0800, John Larkin >> <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sat, 10 Nov 2007 19:55:00 -0600, John Fields >>><jfields(a)austininstruments.com> wrote: >>> >>>>On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson >>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>> >>>>>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin >>>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>>> >>>>>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >>>>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>>>> >>>>>[snip] >>>>>>> >>>>>>>Now please present us with your "solution" with component names >>>>>>>and values and I'll simulate it side-by-side with my design. >>>>>> >>>>>> >>>>>>I rarely simulate. Design is the reverse of simulation. Design >>>>>>forces the desired results, so why simulate? >>>>>> >>>>>[snip] >>>>> >>>>>So you've been converted to the Bob Pease school of hand waving >>>>>?:-) >>>>> >>>>>My POV: Design puts the idea onto paper. Simulation proves that >>>>>what >>>>>is on the paper really works. But simulators don't "design". In >>>>>my business, simulation "proof" is required for each and every >>>>>process corner, otherwise the customer doesn't "buy". >>>> >>>>--- >>>>I used to be in Larkin's corner, defending "build and test" over >>>>"simulate", but after writing a few simulators to solve specific >>>>problems posed here on sed, which couldn't be solved, practically, >>>>any other way, I decided to lay down my wire-wrap gun until the >>>>machine worked in the computer. >>>> >>>>Then, along came wonderful, free LTSPICE. >>>> >>>>I've designed stuff using it which I never had to physically build, >>>>but which worked and which I got paid for, which is a joy. >>>> >>>>A feeling I'm sure you enjoyed before I did. :-) >>> >>>An asynchronous circuit like this, and even moreso some of the >>>others that gave been posted, has internal delays and is subject to >>>all possible timings in the chatter zone. Spice can't really test >>>all the possible combinations of timings. You can generate a chatter >>>simulator, but you can't be sure its deterministic behavior >>>represents the real world of arbitrary timings. Complex async >>>circuits can have low-probability picosecond-wide windows of hazard. >>> >>>John >> >> I got inspired by that differentiator + schmitt invertor sketch of >> yours. >> The idea was to move the signal into the hysteresis levels. >> I though I'd try doing the opposite..Moving the hystersis levels to >> meet the signal.. >> >> Check out my hysteretic hairball! :O * >> http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg >> 569Kb >> >> Notes: >> * Top wave is the inverting input of U1. >> (It's a cool waveform. 4 levels! :) ) >> * Prop delay is from a single device at less than 10nS. >> * This can be a 1 chip solution with a fast dual comparator. >> * I picked the LT1713 just because it's fast. >> * The integrator + U2 could be replaced by some 'one shot' IC >> solution * This circuit is not quite baked because I skipped on the >> math and did best guesses on the resistor values. >> >> With some tweaking, I think this might be a good circuit. >> >> D from BC > >I would say the idea is on target the the implementation is >excessively partsy. Simplify. I might put it back in the oven for more cooking but I dunno yet...I might switch meals :) D from BC
From: D from BC on 11 Nov 2007 20:07
On Sun, 11 Nov 2007 15:54:49 -0800, JosephKK <joseph_barrett(a)sbcglobal.net> wrote: >D from BC myrealaddress(a)comic.com posted to sci.electronics.design: > >> On Sun, 11 Nov 2007 08:29:44 -0700, Jim Thompson >> <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >> >>>On Sat, 10 Nov 2007 19:55:00 -0600, John Fields >>><jfields(a)austininstruments.com> wrote: >>> >>>>On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson >>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>> >>>>>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin >>>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>>> >>>>>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >>>>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>>>> >>>>>[snip] >>>>>>> >>>>>>>Now please present us with your "solution" with component names >>>>>>>and values and I'll simulate it side-by-side with my design. >>>>>> >>>>>> >>>>>>I rarely simulate. Design is the reverse of simulation. Design >>>>>>forces the desired results, so why simulate? >>>>>> >>>>>[snip] >>>>> >>>>>So you've been converted to the Bob Pease school of hand waving >>>>>?:-) >>>>> >>>>>My POV: Design puts the idea onto paper. Simulation proves that >>>>>what >>>>>is on the paper really works. But simulators don't "design". In >>>>>my business, simulation "proof" is required for each and every >>>>>process corner, otherwise the customer doesn't "buy". >>>> >>>>--- >>>>I used to be in Larkin's corner, defending "build and test" over >>>>"simulate", but after writing a few simulators to solve specific >>>>problems posed here on sed, which couldn't be solved, practically, >>>>any other way, I decided to lay down my wire-wrap gun until the >>>>machine worked in the computer. >>>> >>>>Then, along came wonderful, free LTSPICE. >>>> >>>>I've designed stuff using it which I never had to physically build, >>>>but which worked and which I got paid for, which is a joy. >>>> >>>>A feeling I'm sure you enjoyed before I did. :-) >>> >>>It took me MANY years to trust simulators. Initially even bipolar >>>device models were bad. >>> >>>But I still "design" by first "sketching", even if the "sketching" >>>does use a schematic capture program... I'm faster that way, no >>>erasing... drag stuff around... such fun! >>> >>>Then I simulate. >>> >>> ...Jim Thompson >> >> I still sketch for the tough problems. >> That gives me the freedom to express the problem in any fashion. >> If drawing cartoons of a little choo choo train stuck in a valley >> helps to solve the circuit ... great! :) >> >> Also, I think I can move my pen faster than a mouse. >> D from BC > >Yeah, but my pen (when using the tablet) can move a symbol or even a >group of symbols. I've been so tempted to get a tablet.. I just don't like the prices I see at the computer shops.. (Doh... I'm forgetting Eprey (Ebay) again.. :P ) Is it the trendy thing to have for electronics design nowadays? D from BC |