Debouncing....at About 1Mhz - Uobtanium Obtained ;-)
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From: John Fields on 11 Nov 2007 13:26 On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Sun, 11 Nov 2007 01:32:07 -0800, D from BC ><myrealaddress(a)comic.com> wrote: >>Check out my hysteretic hairball! :O * >>http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg >>569Kb > >Yeah, I was thinking along those lines. This is a "feed-beside" sort >of concept, a brutally fast forward path, with slower tweaks off to >the side to fix the low-speed defects. This was the concept Tek used >in their 7000 series oscilloscopes. > >I was also thinking that the origical hysteresis idea was OK except >that the hyst band of cmos schmitts is poorly defined. That's fixable >by defining it better, namely by adding additional hysteresis. The >numbers ought to work. --- I think this pretty much takes care of it all. Version 4 SHEET 1 1700 680 WIRE 688 -336 496 -336 WIRE 368 -304 16 -304 WIRE 576 -304 368 -304 WIRE 368 -256 368 -304 WIRE 336 -240 192 -240 WIRE 576 -240 576 -304 WIRE 496 -224 496 -336 WIRE 496 -224 400 -224 WIRE 544 -224 496 -224 WIRE -256 -208 -304 -208 WIRE -128 -208 -176 -208 WIRE 336 -208 -128 -208 WIRE 688 -208 608 -208 WIRE 544 -192 448 -192 WIRE 192 -128 192 -240 WIRE 256 -128 192 -128 WIRE 688 -128 688 -208 WIRE 688 -128 320 -128 WIRE -128 -32 -128 -208 WIRE -80 -32 -128 -32 WIRE 16 -32 16 -304 WIRE 16 -32 0 -32 WIRE -128 0 -128 -32 WIRE 16 0 16 -32 WIRE 240 0 16 0 WIRE 448 0 448 -192 WIRE 448 0 320 0 WIRE 448 16 448 0 WIRE 480 16 448 16 WIRE 576 16 576 -176 WIRE 576 16 544 16 WIRE 16 64 16 0 WIRE 64 64 16 64 WIRE 192 64 192 -128 WIRE 192 64 144 64 WIRE 448 64 448 16 WIRE 192 96 192 64 WIRE 16 112 16 64 WIRE -128 224 -128 80 WIRE 16 224 16 192 WIRE 16 224 -128 224 WIRE 192 224 192 176 WIRE 192 224 16 224 WIRE 368 224 368 -192 WIRE 368 224 192 224 WIRE 448 224 448 144 WIRE 448 224 368 224 WIRE 576 224 576 16 WIRE 576 224 448 224 WIRE -128 288 -128 224 FLAG -128 288 0 SYMBOL Comparators\\LT1720 368 -288 R0 WINDOW 0 33 88 Left 0 WINDOW 3 26 41 Left 0 SYMATTR InstName U1 SYMBOL voltage 16 96 R0 WINDOW 123 0 0 Left 0 WINDOW 39 0 0 Left 0 WINDOW 0 -69 53 Left 0 WINDOW 3 -62 78 Left 0 SYMATTR InstName V2 SYMATTR Value 5 SYMBOL res 160 48 R90 WINDOW 0 64 56 VBottom 0 WINDOW 3 66 56 VTop 0 SYMATTR InstName R6 SYMATTR Value 10k SYMBOL cap 320 -144 R90 WINDOW 0 66 31 VBottom 0 WINDOW 3 70 33 VTop 0 SYMATTR InstName C3 SYMATTR Value 1e-10 SYMBOL Comparators\\LT1720 576 -272 R0 WINDOW 0 33 88 Left 0 WINDOW 3 26 41 Left 0 SYMATTR InstName U2 SYMBOL res 208 192 R180 WINDOW 0 -47 72 Left 0 WINDOW 3 -51 44 Left 0 SYMATTR InstName R1 SYMATTR Value 10k SYMBOL res 464 160 R180 WINDOW 0 44 70 Left 0 WINDOW 3 36 40 Left 0 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL res 336 -16 R90 WINDOW 0 64 58 VBottom 0 WINDOW 3 71 59 VTop 0 SYMATTR InstName R3 SYMATTR Value 10k SYMBOL cap 544 0 R90 WINDOW 0 64 31 VBottom 0 WINDOW 3 65 31 VTop 0 SYMATTR InstName C1 SYMATTR Value 1e-9 SYMBOL res -272 -192 R270 WINDOW 0 70 59 VTop 0 WINDOW 3 67 58 VBottom 0 SYMATTR InstName R5 SYMATTR Value 750 SYMBOL res -112 96 R180 WINDOW 0 -40 64 Left 0 WINDOW 3 -52 34 Left 0 SYMATTR InstName R7 SYMATTR Value 1000 SYMBOL res -96 -16 R270 WINDOW 0 71 56 VTop 0 WINDOW 3 65 54 VBottom 0 SYMATTR InstName R8 SYMATTR Value 1000 TEXT -112 256 Left 0 !.tran 10e-6 uic TEXT -336 -208 Left 0 ;IN TEXT 696 -336 Left 0 ;OUT -- JF
From: D from BC on 11 Nov 2007 13:40 On Sun, 11 Nov 2007 08:29:44 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >On Sat, 10 Nov 2007 19:55:00 -0600, John Fields ><jfields(a)austininstruments.com> wrote: > >>On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson >><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >> >>>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin >>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>> >>>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>> >>>[snip] >>>>> >>>>>Now please present us with your "solution" with component names and >>>>>values and I'll simulate it side-by-side with my design. >>>> >>>> >>>>I rarely simulate. Design is the reverse of simulation. Design forces >>>>the desired results, so why simulate? >>>> >>>[snip] >>> >>>So you've been converted to the Bob Pease school of hand waving ?:-) >>> >>>My POV: Design puts the idea onto paper. Simulation proves that what >>>is on the paper really works. But simulators don't "design". In my >>>business, simulation "proof" is required for each and every process >>>corner, otherwise the customer doesn't "buy". >> >>--- >>I used to be in Larkin's corner, defending "build and test" over >>"simulate", but after writing a few simulators to solve specific >>problems posed here on sed, which couldn't be solved, practically, >>any other way, I decided to lay down my wire-wrap gun until the >>machine worked in the computer. >> >>Then, along came wonderful, free LTSPICE. >> >>I've designed stuff using it which I never had to physically build, >>but which worked and which I got paid for, which is a joy. >> >>A feeling I'm sure you enjoyed before I did. :-) > >It took me MANY years to trust simulators. Initially even bipolar >device models were bad. > >But I still "design" by first "sketching", even if the "sketching" >does use a schematic capture program... I'm faster that way, no >erasing... drag stuff around... such fun! > >Then I simulate. > > ...Jim Thompson I still sketch for the tough problems. That gives me the freedom to express the problem in any fashion. If drawing cartoons of a little choo choo train stuck in a valley helps to solve the circuit ... great! :) Also, I think I can move my pen faster than a mouse. D from BC
From: John Larkin on 11 Nov 2007 14:34 On Sun, 11 Nov 2007 08:25:59 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > >Think of the XOR as a device that is switched from being an inverter >to being a buffer. The switching does not occur while clock (input) >edges are present. > >>And the input can chatter, or it > >Does nothing after the first transition... it's an edge-triggered >flop. > >>could be a single edge of either polarity. All those conditions have >>to be proven to work, and proving it is too much work. >> >>I avoid clever stuff like that, in hardware and in software. Sorry, >>but I prefer my first circuit, because it's a lot easier to >>understand. >> >>John > >When I feel confused I drinks a glass of wine ;-) > > ...Jim Thompson Coffee works better for me. OK, how about this? http://img225.imageshack.us/my.php?image=catchernv0.jpg John
From: D from BC on 11 Nov 2007 14:45 On Sun, 11 Nov 2007 12:26:01 -0600, John Fields <jfields(a)austininstruments.com> wrote: >On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin ><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>On Sun, 11 Nov 2007 01:32:07 -0800, D from BC >><myrealaddress(a)comic.com> wrote: > >>>Check out my hysteretic hairball! :O * >>>http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg >>>569Kb >> >>Yeah, I was thinking along those lines. This is a "feed-beside" sort >>of concept, a brutally fast forward path, with slower tweaks off to >>the side to fix the low-speed defects. This was the concept Tek used >>in their 7000 series oscilloscopes. >> >>I was also thinking that the origical hysteresis idea was OK except >>that the hyst band of cmos schmitts is poorly defined. That's fixable >>by defining it better, namely by adding additional hysteresis. The >>numbers ought to work. > >--- >I think this pretty much takes care of it all. > [snipped .asc file for less scrolling] Yup ..this is in the same solution family. Without running a sim, I can see how this works.. It's comparator reference level shifting by differentiator. The differentiator pops the - input into oblivion for a time which makes the comparator dead and that's how the fuzzy edges are skipped. Nice.... Uses single output op amps. Single device prop delay. 1 IC solution. Fast. I like my 80% baked solution on http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg The first op amp is unstable. When an edge crosses the threshold the comparator locks up fast due to a local positive feedback loop. The input signal probably can't compete with this and therefore no race condition exists and it's unlikely the timing will fault. (Yes...I got scared by JL posts of asynch hairballs. :) ) JF, I see a 2 comparator delay in disabling the first comparator. I have to wonder if some glitch could still slip through.. In my circuit the first comparator is disabled by 1 comparator delay. D from BC
From: John Larkin on 11 Nov 2007 16:00
On Sun, 11 Nov 2007 12:26:01 -0600, John Fields <jfields(a)austininstruments.com> wrote: >On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin ><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>On Sun, 11 Nov 2007 01:32:07 -0800, D from BC >><myrealaddress(a)comic.com> wrote: > >>>Check out my hysteretic hairball! :O * >>>http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg >>>569Kb >> >>Yeah, I was thinking along those lines. This is a "feed-beside" sort >>of concept, a brutally fast forward path, with slower tweaks off to >>the side to fix the low-speed defects. This was the concept Tek used >>in their 7000 series oscilloscopes. >> >>I was also thinking that the origical hysteresis idea was OK except >>that the hyst band of cmos schmitts is poorly defined. That's fixable >>by defining it better, namely by adding additional hysteresis. The >>numbers ought to work. > >--- >I think this pretty much takes care of it all. Looks pretty good. The only hazard I can see is that a very fast spike can blow through the first comparator before the second one has time to come back around. That's a hazard with most all comparators that have external hysteresis. That's only a problem if the input can in fact have such fast spikes, which in this case maybe it can't. John |