Debouncing....at About 1Mhz - Uobtanium Obtained ;-)
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From: John Fields on 11 Nov 2007 17:33 On Sun, 11 Nov 2007 13:07:10 -0800, D from BC <myrealaddress(a)comic.com> wrote: >On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin ><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>On Sun, 11 Nov 2007 01:32:07 -0800, D from BC >><myrealaddress(a)comic.com> wrote: >> >>>On Sat, 10 Nov 2007 19:35:26 -0800, John Larkin >>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>> >>>>On Sat, 10 Nov 2007 19:55:00 -0600, John Fields >>>><jfields(a)austininstruments.com> wrote: >>>> >>>>>On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson >>>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>>> >>>>>>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin >>>>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>>>> >>>>>>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >>>>>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>>>>> >>>>>>[snip] >>>>>>>> >>>>>>>>Now please present us with your "solution" with component names and >>>>>>>>values and I'll simulate it side-by-side with my design. >>>>>>> >>>>>>> >>>>>>>I rarely simulate. Design is the reverse of simulation. Design forces >>>>>>>the desired results, so why simulate? >>>>>>> >>>>>>[snip] >>>>>> >>>>>>So you've been converted to the Bob Pease school of hand waving ?:-) >>>>>> >>>>>>My POV: Design puts the idea onto paper. Simulation proves that what >>>>>>is on the paper really works. But simulators don't "design". In my >>>>>>business, simulation "proof" is required for each and every process >>>>>>corner, otherwise the customer doesn't "buy". >>>>> >>>>>--- >>>>>I used to be in Larkin's corner, defending "build and test" over >>>>>"simulate", but after writing a few simulators to solve specific >>>>>problems posed here on sed, which couldn't be solved, practically, >>>>>any other way, I decided to lay down my wire-wrap gun until the >>>>>machine worked in the computer. >>>>> >>>>>Then, along came wonderful, free LTSPICE. >>>>> >>>>>I've designed stuff using it which I never had to physically build, >>>>>but which worked and which I got paid for, which is a joy. >>>>> >>>>>A feeling I'm sure you enjoyed before I did. :-) >>>> >>>>An asynchronous circuit like this, and even moreso some of the others >>>>that gave been posted, has internal delays and is subject to all >>>>possible timings in the chatter zone. Spice can't really test all the >>>>possible combinations of timings. You can generate a chatter >>>>simulator, but you can't be sure its deterministic behavior represents >>>>the real world of arbitrary timings. Complex async circuits can have >>>>low-probability picosecond-wide windows of hazard. >>>> >>>>John >>> >>>I got inspired by that differentiator + schmitt invertor sketch of >>>yours. >>>The idea was to move the signal into the hysteresis levels. >>>I though I'd try doing the opposite..Moving the hystersis levels to >>>meet the signal.. >>> >>>Check out my hysteretic hairball! :O * >>>http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg >>>569Kb >> >>Yeah, I was thinking along those lines. This is a "feed-beside" sort >>of concept, a brutally fast forward path, with slower tweaks off to >>the side to fix the low-speed defects. This was the concept Tek used >>in their 7000 series oscilloscopes. >> >>I was also thinking that the origical hysteresis idea was OK except >>that the hyst band of cmos schmitts is poorly defined. That's fixable >>by defining it better, namely by adding additional hysteresis. The >>numbers ought to work. >> >>John >> > >Damn...that's right...This is freakn scope trigger tech... :P >I didn't notice. >Bummer... :( I'm reinventing the wheel again. > >Now I'm wondering if I could have cheated and looked up oscilloscope >trigger circuit patents to dodge a whole lot of dinking with gates, D >ff's and one shots. >There should be ooodles of trigger art since the invention of the >oscilloscope. > >What to do..... >Use time sifting through mountains of patents >versus >use time designing from scratch.. --- If it's for your own enlightenment, design from scratch. That way, if you succeed, the thrill of discovery will be yours as much as it was for whoever came up with it first, if you weren't. And, if you fail, you will have, at least, fought the good fight. :-) -- JF
From: D from BC on 11 Nov 2007 17:46 On Sun, 11 Nov 2007 14:20:54 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >On Sun, 11 Nov 2007 13:07:10 -0800, D from BC ><myrealaddress(a)comic.com> wrote: > >>On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >[snip] >>> >>>I was also thinking that the origical hysteresis idea was OK except >>>that the hyst band of cmos schmitts is poorly defined. That's fixable >>>by defining it better, namely by adding additional hysteresis. The >>>numbers ought to work. >>> >>>John >>> >> >>Damn...that's right...This is freakn scope trigger tech... :P >>I didn't notice. >>Bummer... :( I'm reinventing the wheel again. >> >>Now I'm wondering if I could have cheated and looked up oscilloscope >>trigger circuit patents to dodge a whole lot of dinking with gates, D >>ff's and one shots. >>There should be ooodles of trigger art since the invention of the >>oscilloscope. > >Well, DUH! My circuit trips on the first edge and ignores all others >"until sweep is complete"... it's called BLANKING ;-) > >> >>What to do..... >>Use time sifting through mountains of patents >>versus >>use time designing from scratch.. >> >> >>D from BC > > ...Jim Thompson lol... When I first posted this problem (Debouncing....at About 1Mhz). I did suspect it was a classic problem with a known classic solution. I just didn't think of in what... Oscilloscopes! Doh! :( About all schematics... The thing I don't like about the use of comparator solutions is a bucketload of resistors are needed as seen in my design and JF's design. The JL based 2 D ff + one shot I posted has a lower parts count and the same goes for your (Jim) recently posted schematics. All with only 1 Dff prop delay off the primary pos edge and primary neg edge. It looks like it's down to D flip flops vs comparators. I like the parts count of Dff based designs and I'm going to look at'm closer.. D from BC
From: JosephKK on 11 Nov 2007 18:14 Jim Thompson To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com posted to sci.electronics.design: > On Sun, 11 Nov 2007 08:25:59 -0700, Jim Thompson > <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > >>On Sat, 10 Nov 2007 17:44:09 -0800, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sat, 10 Nov 2007 18:03:07 -0700, Jim Thompson >>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>> >>>>On Sat, 10 Nov 2007 16:19:54 -0800, John Larkin >>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> >>[snip] >>>>>>> >>>>>>>Your Sysreset sets Q high, but your sim starts with Q low. Why? >>>>>>> >>>>>>>John >>>>>>> >>>>>> >>>>>>The default set-ups included FF initial conditions Q=0. If I >>>>>>uncheck that box it starts, as would be expected, with Q=1. >>>>>> >>>>>> ...Jim Thompson >>>>> >>>>>Well, run that. It's more interesting. >>>>> >>>>>John >>>> >>>>Yep. It takes one cycle for the output to be correct. >>>> >>>> ...Jim Thompson >>> >>> >>>It seems to work, but it's awfully convoluted. It would be, for me, >>>like one of those things that I designed but that I can barely >>>understand myself; there are too many possible states, and the >>>dflop clock sometimes comes from the input, and sometimes comes >>>from the input xored with the internal delay. >> >>Think of the XOR as a device that is switched from being an inverter >>to being a buffer. The switching does not occur while clock (input) >>edges are present. >> >>>And the input can chatter, or it >> >>Does nothing after the first transition... it's an edge-triggered >>flop. >> >>>could be a single edge of either polarity. All those conditions >>>have to be proven to work, and proving it is too much work. >>> >>>I avoid clever stuff like that, in hardware and in software. Sorry, >>>but I prefer my first circuit, because it's a lot easier to >>>understand. >>> >>>John >> >>When I feel confused I drinks a glass of wine ;-) >> >> ...Jim Thompson > > With PREbar functional.... > > http://www.analog-innovations.com/SED/AlternatingEdge-Unobtanium.pdf > > I use that inverter/buffer characteristic of the XOR a lot... > > Say I have an 8GHz (Johnson-type) divider chain down to 125MHz... > object to create single-side-band. (Mixed-mode to boot... CML down > to around 500MHZ, then CMOS.) > > Since it's a Johnson counter with no set or reset, how do I > guarantee the phase relationship of the 8GHz to the 125MHz? > > Answer, I don't. > > What I did was measure literally, using a cell aptly named > "WhosOnFirst.sch" (*) and invert as needed. > > (*) No one got the joke. Youngsters :-( > > ...Jim Thompson Damnit, are you trying to make feel old. Today is catching.
From: Jim Thompson on 11 Nov 2007 18:28 On Sun, 11 Nov 2007 23:14:15 GMT, JosephKK <joseph_barrett(a)sbcglobal.net> wrote: >Jim Thompson To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com posted to >sci.electronics.design: > [snip] >> >> What I did was measure literally, using a cell aptly named >> "WhosOnFirst.sch" (*) and invert as needed. >> >> (*) No one got the joke. Youngsters :-( >> >> ...Jim Thompson > >Damnit, are you trying to make feel old. >Today is catching. Sno-o-o-ort! ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | America: Land of the Free, Because of the Brave
From: JosephKK on 11 Nov 2007 18:30
ChairmanOfTheBored RUBored(a)crackasmile.org posted to sci.electronics.design: > On Sat, 10 Nov 2007 19:07:16 -0800, D from BC > <myrealaddress(a)comic.com> wrote: > >>On Sat, 10 Nov 2007 19:55:00 -0600, John Fields >><jfields(a)austininstruments.com> wrote: >> >>>On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson >>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>> >>>>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin >>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> >>>>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >>>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>>> >>>>[snip] >>>>>> >>>>>>Now please present us with your "solution" with component names >>>>>>and values and I'll simulate it side-by-side with my design. >>>>> >>>>> >>>>>I rarely simulate. Design is the reverse of simulation. Design >>>>>forces the desired results, so why simulate? >>>>> >>>>[snip] >>>> >>>>So you've been converted to the Bob Pease school of hand waving >>>>?:-) >>>> >>>>My POV: Design puts the idea onto paper. Simulation proves that >>>>what >>>>is on the paper really works. But simulators don't "design". In >>>>my business, simulation "proof" is required for each and every >>>>process corner, otherwise the customer doesn't "buy". >>> >>>--- >>>I used to be in Larkin's corner, defending "build and test" over >>>"simulate", but after writing a few simulators to solve specific >>>problems posed here on sed, which couldn't be solved, practically, >>>any other way, I decided to lay down my wire-wrap gun until the >>>machine worked in the computer. >>> >>>Then, along came wonderful, free LTSPICE. >>> >>>I've designed stuff using it which I never had to physically build, >>>but which worked and which I got paid for, which is a joy. >>> >>>A feeling I'm sure you enjoyed before I did. :-) >> >>I still find it amazing that after benchtesting, I can see that I >>forgot to include parasitics in a circuit model. >>After including the parasitics in the model, I get the sim waveforms >>that I see on the scope :) >> >>Bouncing between model and bench and model and bench can build a >>good model. > > > > Forgetting the parasitic aspects of circuit configurations as well > as > the individual components themselves is the main reason why those > that do > not like simulators hate to use them. They fail at doing so. > > A good sim will match the real circuit just about exactly. > Considering > the elements of the software used to make a sim a sim, it would have > to. > > It's like Ohm's Law. The rules are the rules, and if you are > following > them, your calculator will display the proper figure in its > mantissa. > > Sims work great. I love 'em. When they don't match the real data > gathered, and the engineer goes about the chore of finding out why, > he > should also increase his education in the field as a result. A > proper > sim will always match the real data. If it doesn't, something was > left > out. It is like a puzzle. Goodness, 4 paragraphs and not a curse word in it. You even seem to make sense this time. If you post like this you could be welcome here. |