Debouncing....at About 1Mhz - Uobtanium Obtained ;-)
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From: D from BC on 11 Nov 2007 16:07 On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Sun, 11 Nov 2007 01:32:07 -0800, D from BC ><myrealaddress(a)comic.com> wrote: > >>On Sat, 10 Nov 2007 19:35:26 -0800, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sat, 10 Nov 2007 19:55:00 -0600, John Fields >>><jfields(a)austininstruments.com> wrote: >>> >>>>On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson >>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>> >>>>>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin >>>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>>> >>>>>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >>>>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>>>> >>>>>[snip] >>>>>>> >>>>>>>Now please present us with your "solution" with component names and >>>>>>>values and I'll simulate it side-by-side with my design. >>>>>> >>>>>> >>>>>>I rarely simulate. Design is the reverse of simulation. Design forces >>>>>>the desired results, so why simulate? >>>>>> >>>>>[snip] >>>>> >>>>>So you've been converted to the Bob Pease school of hand waving ?:-) >>>>> >>>>>My POV: Design puts the idea onto paper. Simulation proves that what >>>>>is on the paper really works. But simulators don't "design". In my >>>>>business, simulation "proof" is required for each and every process >>>>>corner, otherwise the customer doesn't "buy". >>>> >>>>--- >>>>I used to be in Larkin's corner, defending "build and test" over >>>>"simulate", but after writing a few simulators to solve specific >>>>problems posed here on sed, which couldn't be solved, practically, >>>>any other way, I decided to lay down my wire-wrap gun until the >>>>machine worked in the computer. >>>> >>>>Then, along came wonderful, free LTSPICE. >>>> >>>>I've designed stuff using it which I never had to physically build, >>>>but which worked and which I got paid for, which is a joy. >>>> >>>>A feeling I'm sure you enjoyed before I did. :-) >>> >>>An asynchronous circuit like this, and even moreso some of the others >>>that gave been posted, has internal delays and is subject to all >>>possible timings in the chatter zone. Spice can't really test all the >>>possible combinations of timings. You can generate a chatter >>>simulator, but you can't be sure its deterministic behavior represents >>>the real world of arbitrary timings. Complex async circuits can have >>>low-probability picosecond-wide windows of hazard. >>> >>>John >> >>I got inspired by that differentiator + schmitt invertor sketch of >>yours. >>The idea was to move the signal into the hysteresis levels. >>I though I'd try doing the opposite..Moving the hystersis levels to >>meet the signal.. >> >>Check out my hysteretic hairball! :O * >>http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg >>569Kb > >Yeah, I was thinking along those lines. This is a "feed-beside" sort >of concept, a brutally fast forward path, with slower tweaks off to >the side to fix the low-speed defects. This was the concept Tek used >in their 7000 series oscilloscopes. > >I was also thinking that the origical hysteresis idea was OK except >that the hyst band of cmos schmitts is poorly defined. That's fixable >by defining it better, namely by adding additional hysteresis. The >numbers ought to work. > >John > Damn...that's right...This is freakn scope trigger tech... :P I didn't notice. Bummer... :( I'm reinventing the wheel again. Now I'm wondering if I could have cheated and looked up oscilloscope trigger circuit patents to dodge a whole lot of dinking with gates, D ff's and one shots. There should be ooodles of trigger art since the invention of the oscilloscope. What to do..... Use time sifting through mountains of patents versus use time designing from scratch.. D from BC
From: Jim Thompson on 11 Nov 2007 16:16 On Sun, 11 Nov 2007 11:34:35 -0800, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Sun, 11 Nov 2007 08:25:59 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > > >> >>Think of the XOR as a device that is switched from being an inverter >>to being a buffer. The switching does not occur while clock (input) >>edges are present. >> >>>And the input can chatter, or it >> >>Does nothing after the first transition... it's an edge-triggered >>flop. >> >>>could be a single edge of either polarity. All those conditions have >>>to be proven to work, and proving it is too much work. >>> >>>I avoid clever stuff like that, in hardware and in software. Sorry, >>>but I prefer my first circuit, because it's a lot easier to >>>understand. >>> >>>John >> >>When I feel confused I drinks a glass of wine ;-) >> >> ...Jim Thompson > >Coffee works better for me. > >OK, how about this? > >http://img225.imageshack.us/my.php?image=catchernv0.jpg > > >John I found, at least with 74HC' stuff, that I needed to delay the clock flip-over as well... looked like SUAH timing was violated. ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | America: Land of the Free, Because of the Brave
From: Jim Thompson on 11 Nov 2007 16:20 On Sun, 11 Nov 2007 13:07:10 -0800, D from BC <myrealaddress(a)comic.com> wrote: >On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin ><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > [snip] >> >>I was also thinking that the origical hysteresis idea was OK except >>that the hyst band of cmos schmitts is poorly defined. That's fixable >>by defining it better, namely by adding additional hysteresis. The >>numbers ought to work. >> >>John >> > >Damn...that's right...This is freakn scope trigger tech... :P >I didn't notice. >Bummer... :( I'm reinventing the wheel again. > >Now I'm wondering if I could have cheated and looked up oscilloscope >trigger circuit patents to dodge a whole lot of dinking with gates, D >ff's and one shots. >There should be ooodles of trigger art since the invention of the >oscilloscope. Well, DUH! My circuit trips on the first edge and ignores all others "until sweep is complete"... it's called BLANKING ;-) > >What to do..... >Use time sifting through mountains of patents >versus >use time designing from scratch.. > > >D from BC ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | America: Land of the Free, Because of the Brave
From: John Fields on 11 Nov 2007 17:06 On Sun, 11 Nov 2007 11:45:38 -0800, D from BC <myrealaddress(a)comic.com> wrote: >On Sun, 11 Nov 2007 12:26:01 -0600, John Fields ><jfields(a)austininstruments.com> wrote: > >>On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sun, 11 Nov 2007 01:32:07 -0800, D from BC >>><myrealaddress(a)comic.com> wrote: >> >>>>Check out my hysteretic hairball! :O * >>>>http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg >>>>569Kb >>> >>>Yeah, I was thinking along those lines. This is a "feed-beside" sort >>>of concept, a brutally fast forward path, with slower tweaks off to >>>the side to fix the low-speed defects. This was the concept Tek used >>>in their 7000 series oscilloscopes. >>> >>>I was also thinking that the origical hysteresis idea was OK except >>>that the hyst band of cmos schmitts is poorly defined. That's fixable >>>by defining it better, namely by adding additional hysteresis. The >>>numbers ought to work. >> >>--- >>I think this pretty much takes care of it all. >> >[snipped .asc file for less scrolling] > >Yup ..this is in the same solution family. > >Without running a sim, I can see how this works.. >It's comparator reference level shifting by differentiator. >The differentiator pops the - input into oblivion for a time which >makes the comparator dead and that's how the fuzzy edges are skipped. --- Actually, the input signal is attenuated so that it toggles between 1.5V and 3.5V, (so that one of the inputs is always below the common mode limit) and the differentiator forces the inverting input of the comparator to a little bit higher/lower than the rail with the opposite polarity of the input signal, which keeps the input chatter away from the switching point until the cap discharges. --- >Nice.... --- Thanks! :-) --- >Uses single output op amps. --- Comparators. --- >Single device prop delay. >1 IC solution. >Fast. --- Yup. Tpd = 8ns worst case over temp., 6.5 ns at room temp. --- >I like my 80% baked solution on >http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg --- Yeah, not bad for a newbie ;) Not bad at all, for that matter. :-) --- >The first op amp --- comparator --- >is unstable. When an edge crosses the threshold the >comparator locks up fast due to a local positive feedback loop. >The input signal probably can't compete with this --- Probably ??? You're the designer, how come you don't know for sure? --- > and therefore no >race condition exists and it's unlikely the timing will fault. >(Yes...I got scared by JL posts of asynch hairballs. :) ) --- Don't be afraid. JL is a good circuit designer, but he has his own agenda. --- >JF, I see a 2 comparator delay in disabling the first comparator. >I have to wonder if some glitch could still slip through.. --- It might, but it would have to be pretty damn fast. If you know what the signal looks like, worst case, during the early switching interval, or if you can spec the glitch time, then maybe we can come up with a bulletproof solution for you. Do/can you? --- >In my circuit the first comparator is disabled by 1 comparator delay. --- Ah... But how long does it take to get through? ;) -- JF
From: John Larkin on 11 Nov 2007 17:08
On Sun, 11 Nov 2007 16:06:27 -0600, John Fields <jfields(a)austininstruments.com> wrote: >> and therefore no >>race condition exists and it's unlikely the timing will fault. >>(Yes...I got scared by JL posts of asynch hairballs. :) ) > >--- >Don't be afraid. JL is a good circuit designer, but he has his own >agenda. Yeah. I hate to write ECOs. John |