Debouncing....at About 1Mhz - Uobtanium Obtained ;-)
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From: John Larkin on 11 Nov 2007 11:19 On Sun, 11 Nov 2007 09:01:37 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >On Sun, 11 Nov 2007 08:25:59 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > >>On Sat, 10 Nov 2007 17:44:09 -0800, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sat, 10 Nov 2007 18:03:07 -0700, Jim Thompson >>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>> >>>>On Sat, 10 Nov 2007 16:19:54 -0800, John Larkin >>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> >>[snip] >>>>>>> >>>>>>>Your Sysreset sets Q high, but your sim starts with Q low. Why? >>>>>>> >>>>>>>John >>>>>>> >>>>>> >>>>>>The default set-ups included FF initial conditions Q=0. If I uncheck >>>>>>that box it starts, as would be expected, with Q=1. >>>>>> >>>>>> ...Jim Thompson >>>>> >>>>>Well, run that. It's more interesting. >>>>> >>>>>John >>>> >>>>Yep. It takes one cycle for the output to be correct. >>>> >>>> ...Jim Thompson >>> >>> >>>It seems to work, but it's awfully convoluted. It would be, for me, >>>like one of those things that I designed but that I can barely >>>understand myself; there are too many possible states, and the dflop >>>clock sometimes comes from the input, and sometimes comes from the >>>input xored with the internal delay. >> >>Think of the XOR as a device that is switched from being an inverter >>to being a buffer. The switching does not occur while clock (input) >>edges are present. >> >>>And the input can chatter, or it >> >>Does nothing after the first transition... it's an edge-triggered >>flop. >> >>>could be a single edge of either polarity. All those conditions have >>>to be proven to work, and proving it is too much work. >>> >>>I avoid clever stuff like that, in hardware and in software. Sorry, >>>but I prefer my first circuit, because it's a lot easier to >>>understand. >>> >>>John >> >>When I feel confused I drinks a glass of wine ;-) >> >> ...Jim Thompson > >With PREbar functional.... > >http://www.analog-innovations.com/SED/AlternatingEdge-Unobtanium.pdf > >I use that inverter/buffer characteristic of the XOR a lot... > >Say I have an 8GHz (Johnson-type) divider chain down to 125MHz... >object to create single-side-band. (Mixed-mode to boot... CML down to >around 500MHZ, then CMOS.) > >Since it's a Johnson counter with no set or reset, how do I guarantee >the phase relationship of the 8GHz to the 125MHz? > >Answer, I don't. > >What I did was measure literally, using a cell aptly named >"WhosOnFirst.sch" (*) and invert as needed. > >(*) No one got the joke. Youngsters :-( > > ...Jim Thompson I've done that in Manchester-coded optical systems. If the uP doesn't see good data frames for a while, it sets a bit to xor the data stream, and sets another bit to open up the pll filter bandwidth. John
From: Jim Thompson on 11 Nov 2007 11:22 On Sun, 11 Nov 2007 08:15:14 -0800, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Sun, 11 Nov 2007 09:05:43 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > [snip] >> >>I've been known to toss designs that I had been working for >>weeks/months, because of too many "patches". >> >>Panics the hell out of clients until they see the results of a clean >>start. >> >> ...Jim Thompson > > >It takes guts to dump something you've put three months into. Even if >the new thing would be better and finished sooner. It's even more >difficult in a team design, where peer pressure exists. But yeah, I'll >consider dumping a design that's far along, even finished, when a >better or simpler idea pops up, or when the original starts creaking >of its own weight. > >That's why it's better to not start too soon, to play with ideas for a >while at the start. > >John My wife says I have the Michelangelo syndrome, with the Pope (aka the client) saying, "When will you make an end?" I'm always striving for that simple perfect work of art ;-) ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | America: Land of the Free, Because of the Brave
From: Michael A. Terrell on 11 Nov 2007 11:58 Jim Thompson wrote: > > What I did was measure literally, using a cell aptly named > "WhosOnFirst.sch" (*) and invert as needed. http://www.baseball-almanac.com/humor4.shtml -- Service to my country? Been there, Done that, and I've got my DD214 to prove it. Member of DAV #85. Michael A. Terrell Central Florida
From: Michael A. Terrell on 11 Nov 2007 12:00 Jim Thompson wrote: > > On Sat, 10 Nov 2007 19:55:00 -0600, John Fields > <jfields(a)austininstruments.com> wrote: > > >On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson > ><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > > > >>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin > >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >> > >>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson > >>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > >>> > >>[snip] > >>>> > >>>>Now please present us with your "solution" with component names and > >>>>values and I'll simulate it side-by-side with my design. > >>> > >>> > >>>I rarely simulate. Design is the reverse of simulation. Design forces > >>>the desired results, so why simulate? > >>> > >>[snip] > >> > >>So you've been converted to the Bob Pease school of hand waving ?:-) > >> > >>My POV: Design puts the idea onto paper. Simulation proves that what > >>is on the paper really works. But simulators don't "design". In my > >>business, simulation "proof" is required for each and every process > >>corner, otherwise the customer doesn't "buy". > > > >--- > >I used to be in Larkin's corner, defending "build and test" over > >"simulate", but after writing a few simulators to solve specific > >problems posed here on sed, which couldn't be solved, practically, > >any other way, I decided to lay down my wire-wrap gun until the > >machine worked in the computer. > > > >Then, along came wonderful, free LTSPICE. > > > >I've designed stuff using it which I never had to physically build, > >but which worked and which I got paid for, which is a joy. > > > >A feeling I'm sure you enjoyed before I did. :-) > > It took me MANY years to trust simulators. Initially even bipolar > device models were bad. > > But I still "design" by first "sketching", even if the "sketching" > does use a schematic capture program... I'm faster that way, no > erasing... drag stuff around... such fun! You don't drag them, you push them around! ;-) -- Service to my country? Been there, Done that, and I've got my DD214 to prove it. Member of DAV #85. Michael A. Terrell Central Florida
From: John Larkin on 11 Nov 2007 13:19
On Sun, 11 Nov 2007 09:01:37 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >On Sun, 11 Nov 2007 08:25:59 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > >>On Sat, 10 Nov 2007 17:44:09 -0800, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sat, 10 Nov 2007 18:03:07 -0700, Jim Thompson >>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>> >>>>On Sat, 10 Nov 2007 16:19:54 -0800, John Larkin >>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> >>[snip] >>>>>>> >>>>>>>Your Sysreset sets Q high, but your sim starts with Q low. Why? >>>>>>> >>>>>>>John >>>>>>> >>>>>> >>>>>>The default set-ups included FF initial conditions Q=0. If I uncheck >>>>>>that box it starts, as would be expected, with Q=1. >>>>>> >>>>>> ...Jim Thompson >>>>> >>>>>Well, run that. It's more interesting. >>>>> >>>>>John >>>> >>>>Yep. It takes one cycle for the output to be correct. >>>> >>>> ...Jim Thompson >>> >>> >>>It seems to work, but it's awfully convoluted. It would be, for me, >>>like one of those things that I designed but that I can barely >>>understand myself; there are too many possible states, and the dflop >>>clock sometimes comes from the input, and sometimes comes from the >>>input xored with the internal delay. >> >>Think of the XOR as a device that is switched from being an inverter >>to being a buffer. The switching does not occur while clock (input) >>edges are present. >> >>>And the input can chatter, or it >> >>Does nothing after the first transition... it's an edge-triggered >>flop. >> >>>could be a single edge of either polarity. All those conditions have >>>to be proven to work, and proving it is too much work. >>> >>>I avoid clever stuff like that, in hardware and in software. Sorry, >>>but I prefer my first circuit, because it's a lot easier to >>>understand. >>> >>>John >> >>When I feel confused I drinks a glass of wine ;-) >> >> ...Jim Thompson > >With PREbar functional.... > >http://www.analog-innovations.com/SED/AlternatingEdge-Unobtanium.pdf > >I use that inverter/buffer characteristic of the XOR a lot... > >Say I have an 8GHz (Johnson-type) divider chain down to 125MHz... >object to create single-side-band. (Mixed-mode to boot... CML down to >around 500MHZ, then CMOS.) > >Since it's a Johnson counter with no set or reset, how do I guarantee >the phase relationship of the 8GHz to the 125MHz? > >Answer, I don't. > >What I did was measure literally, using a cell aptly named >"WhosOnFirst.sch" (*) and invert as needed. > >(*) No one got the joke. Youngsters :-( > > ...Jim Thompson At the peak of the Beatles era, I designed the "Come Together" circuit for levelling the steam pressures from two boilers that had separate control loops. Did you like my Seesaw Inverter? John |