Debouncing....at About 1Mhz - Uobtanium Obtained ;-)
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From: JosephKK on 11 Nov 2007 18:36 D from BC myrealaddress(a)comic.com posted to sci.electronics.design: > On Sat, 10 Nov 2007 19:35:26 -0800, John Larkin > <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: > >>On Sat, 10 Nov 2007 19:55:00 -0600, John Fields >><jfields(a)austininstruments.com> wrote: >> >>>On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson >>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>> >>>>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin >>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> >>>>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >>>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>>> >>>>[snip] >>>>>> >>>>>>Now please present us with your "solution" with component names >>>>>>and values and I'll simulate it side-by-side with my design. >>>>> >>>>> >>>>>I rarely simulate. Design is the reverse of simulation. Design >>>>>forces the desired results, so why simulate? >>>>> >>>>[snip] >>>> >>>>So you've been converted to the Bob Pease school of hand waving >>>>?:-) >>>> >>>>My POV: Design puts the idea onto paper. Simulation proves that >>>>what >>>>is on the paper really works. But simulators don't "design". In >>>>my business, simulation "proof" is required for each and every >>>>process corner, otherwise the customer doesn't "buy". >>> >>>--- >>>I used to be in Larkin's corner, defending "build and test" over >>>"simulate", but after writing a few simulators to solve specific >>>problems posed here on sed, which couldn't be solved, practically, >>>any other way, I decided to lay down my wire-wrap gun until the >>>machine worked in the computer. >>> >>>Then, along came wonderful, free LTSPICE. >>> >>>I've designed stuff using it which I never had to physically build, >>>but which worked and which I got paid for, which is a joy. >>> >>>A feeling I'm sure you enjoyed before I did. :-) >> >>An asynchronous circuit like this, and even moreso some of the >>others that gave been posted, has internal delays and is subject to >>all possible timings in the chatter zone. Spice can't really test >>all the possible combinations of timings. You can generate a chatter >>simulator, but you can't be sure its deterministic behavior >>represents the real world of arbitrary timings. Complex async >>circuits can have low-probability picosecond-wide windows of hazard. >> >>John > > I got inspired by that differentiator + schmitt invertor sketch of > yours. > The idea was to move the signal into the hysteresis levels. > I though I'd try doing the opposite..Moving the hystersis levels to > meet the signal.. > > Check out my hysteretic hairball! :O * > http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg > 569Kb > > Notes: > * Top wave is the inverting input of U1. > (It's a cool waveform. 4 levels! :) ) > * Prop delay is from a single device at less than 10nS. > * This can be a 1 chip solution with a fast dual comparator. > * I picked the LT1713 just because it's fast. > * The integrator + U2 could be replaced by some 'one shot' IC > solution * This circuit is not quite baked because I skipped on the > math and did best guesses on the resistor values. > > With some tweaking, I think this might be a good circuit. > > D from BC I would say the idea is on target the the implementation is excessively partsy. Simplify.
From: Jim Thompson on 11 Nov 2007 18:43 On Sun, 11 Nov 2007 15:30:53 -0800, JosephKK <joseph_barrett(a)sbcglobal.net> wrote: >ChairmanOfTheBored RUBored(a)crackasmile.org posted to >sci.electronics.design: > [snip] >> >> Forgetting the parasitic aspects of circuit configurations as well >> as >> the individual components themselves is the main reason why those >> that do >> not like simulators hate to use them. They fail at doing so. >> >> A good sim will match the real circuit just about exactly. >> Considering >> the elements of the software used to make a sim a sim, it would have >> to. >> >> It's like Ohm's Law. The rules are the rules, and if you are >> following >> them, your calculator will display the proper figure in its >> mantissa. >> >> Sims work great. I love 'em. When they don't match the real data >> gathered, and the engineer goes about the chore of finding out why, >> he >> should also increase his education in the field as a result. A >> proper >> sim will always match the real data. If it doesn't, something was >> left >> out. It is like a puzzle. > >Goodness, 4 paragraphs and not a curse word in it. You even seem to >make sense this time. If you post like this you could be welcome >here. Amazing! Indeed such commentary is very welcome here. ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | America: Land of the Free, Because of the Brave
From: JosephKK on 11 Nov 2007 18:54 D from BC myrealaddress(a)comic.com posted to sci.electronics.design: > On Sun, 11 Nov 2007 08:29:44 -0700, Jim Thompson > <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > >>On Sat, 10 Nov 2007 19:55:00 -0600, John Fields >><jfields(a)austininstruments.com> wrote: >> >>>On Sat, 10 Nov 2007 14:40:51 -0700, Jim Thompson >>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>> >>>>On Sat, 10 Nov 2007 11:42:31 -0800, John Larkin >>>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> >>>>>On Sat, 10 Nov 2007 11:57:19 -0700, Jim Thompson >>>>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>>>> >>>>[snip] >>>>>> >>>>>>Now please present us with your "solution" with component names >>>>>>and values and I'll simulate it side-by-side with my design. >>>>> >>>>> >>>>>I rarely simulate. Design is the reverse of simulation. Design >>>>>forces the desired results, so why simulate? >>>>> >>>>[snip] >>>> >>>>So you've been converted to the Bob Pease school of hand waving >>>>?:-) >>>> >>>>My POV: Design puts the idea onto paper. Simulation proves that >>>>what >>>>is on the paper really works. But simulators don't "design". In >>>>my business, simulation "proof" is required for each and every >>>>process corner, otherwise the customer doesn't "buy". >>> >>>--- >>>I used to be in Larkin's corner, defending "build and test" over >>>"simulate", but after writing a few simulators to solve specific >>>problems posed here on sed, which couldn't be solved, practically, >>>any other way, I decided to lay down my wire-wrap gun until the >>>machine worked in the computer. >>> >>>Then, along came wonderful, free LTSPICE. >>> >>>I've designed stuff using it which I never had to physically build, >>>but which worked and which I got paid for, which is a joy. >>> >>>A feeling I'm sure you enjoyed before I did. :-) >> >>It took me MANY years to trust simulators. Initially even bipolar >>device models were bad. >> >>But I still "design" by first "sketching", even if the "sketching" >>does use a schematic capture program... I'm faster that way, no >>erasing... drag stuff around... such fun! >> >>Then I simulate. >> >> ...Jim Thompson > > I still sketch for the tough problems. > That gives me the freedom to express the problem in any fashion. > If drawing cartoons of a little choo choo train stuck in a valley > helps to solve the circuit ... great! :) > > Also, I think I can move my pen faster than a mouse. > D from BC Yeah, but my pen (when using the tablet) can move a symbol or even a group of symbols.
From: John Fields on 11 Nov 2007 19:03 On Sun, 11 Nov 2007 13:00:31 -0800, John Larkin <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >On Sun, 11 Nov 2007 12:26:01 -0600, John Fields ><jfields(a)austininstruments.com> wrote: > >>On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin >><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>>On Sun, 11 Nov 2007 01:32:07 -0800, D from BC >>><myrealaddress(a)comic.com> wrote: >> >>>>Check out my hysteretic hairball! :O * >>>>http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg >>>>569Kb >>> >>>Yeah, I was thinking along those lines. This is a "feed-beside" sort >>>of concept, a brutally fast forward path, with slower tweaks off to >>>the side to fix the low-speed defects. This was the concept Tek used >>>in their 7000 series oscilloscopes. >>> >>>I was also thinking that the origical hysteresis idea was OK except >>>that the hyst band of cmos schmitts is poorly defined. That's fixable >>>by defining it better, namely by adding additional hysteresis. The >>>numbers ought to work. >> >>--- >>I think this pretty much takes care of it all. > > >Looks pretty good. The only hazard I can see is that a very fast spike >can blow through the first comparator before the second one has time >to come back around. That's a hazard with most all comparators that >have external hysteresis. --- These have internal hysteresis but, after just a cursory glance, I haven't figured out how to make that work in this application. --- >That's only a problem if the input can in fact have such fast spikes, >which in this case maybe it can't. --- But maybe it can.. I've asked the OP to disclose what the input signal looks like, so maybe we'll be graced with an answer soon. -- JF
From: D from BC on 11 Nov 2007 19:06
On Sun, 11 Nov 2007 16:06:27 -0600, John Fields <jfields(a)austininstruments.com> wrote: >On Sun, 11 Nov 2007 11:45:38 -0800, D from BC ><myrealaddress(a)comic.com> wrote: > >>On Sun, 11 Nov 2007 12:26:01 -0600, John Fields >><jfields(a)austininstruments.com> wrote: >> >>>On Sun, 11 Nov 2007 07:56:21 -0800, John Larkin >>><jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>> >>>>On Sun, 11 Nov 2007 01:32:07 -0800, D from BC >>>><myrealaddress(a)comic.com> wrote: >>> >>>>>Check out my hysteretic hairball! :O * >>>>>http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg >>>>>569Kb >>>> >>>>Yeah, I was thinking along those lines. This is a "feed-beside" sort >>>>of concept, a brutally fast forward path, with slower tweaks off to >>>>the side to fix the low-speed defects. This was the concept Tek used >>>>in their 7000 series oscilloscopes. >>>> >>>>I was also thinking that the origical hysteresis idea was OK except >>>>that the hyst band of cmos schmitts is poorly defined. That's fixable >>>>by defining it better, namely by adding additional hysteresis. The >>>>numbers ought to work. >>> >>>--- >>>I think this pretty much takes care of it all. >>> >>[snipped .asc file for less scrolling] >> >>Yup ..this is in the same solution family. >> >>Without running a sim, I can see how this works.. >>It's comparator reference level shifting by differentiator. >>The differentiator pops the - input into oblivion for a time which >>makes the comparator dead and that's how the fuzzy edges are skipped. > >--- >Actually, the input signal is attenuated so that it toggles between >1.5V and 3.5V, (so that one of the inputs is always below the common >mode limit) and the differentiator forces the inverting input of the >comparator to a little bit higher/lower than the rail with the >opposite polarity of the input signal, which keeps the input chatter >away from the switching point until the cap discharges. >--- > >>Nice.... > >--- >Thanks! :-) >--- > >>Uses single output op amps. > >--- >Comparators. >--- > >>Single device prop delay. >>1 IC solution. >>Fast. > >--- >Yup. Tpd = 8ns worst case over temp., 6.5 ns at room temp. >--- > >>I like my 80% baked solution on >>http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg > >--- >Yeah, not bad for a newbie ;) > >Not bad at all, for that matter. :-) >--- > >>The first op amp > >--- >comparator >--- > >>is unstable. When an edge crosses the threshold the >>comparator locks up fast due to a local positive feedback loop. >>The input signal probably can't compete with this > >--- >Probably ??? >You're the designer, how come you don't know for sure? >--- > >> and therefore no >>race condition exists and it's unlikely the timing will fault. >>(Yes...I got scared by JL posts of asynch hairballs. :) ) > >--- >Don't be afraid. JL is a good circuit designer, but he has his own >agenda. >--- > >>JF, I see a 2 comparator delay in disabling the first comparator. >>I have to wonder if some glitch could still slip through.. > >--- >It might, but it would have to be pretty damn fast. > >If you know what the signal looks like, worst case, during the early >switching interval, or if you can spec the glitch time, then maybe >we can come up with a bulletproof solution for you. > >Do/can you? >--- > >>In my circuit the first comparator is disabled by 1 comparator delay. > >--- >Ah... > >But how long does it take to get through? ;) Thanks for the complement.. I hurt my brain thinking up that circuit.. :) That's why I have 'op amp' and 'comparator' all mixed up :P I don't know if I could have thought of this circuit without seeing JL's RC+schmitt circuit. You asked how long it takes to get through... (You mean the tp performance..) On http://www.members.shaw.ca/chainsaw/SED/compsolution.jpg The desired output edge forms after only 1 comparator delay. Not only is the edge formed by crossing a threshold but also reinforced by regenerative feedback that also starts after 1 comparator delay too. It probably has the same tp performance as your circuit when using same comparators. The difference might be with input overdrive. I recall seeing input overdrive specs on comparator datasheets. The more overdrive...the less tp. With positive feedback...there's overdrive :) So I suspect the positive feedback will push the comparator to react quicker. D from BC |