FPGA
in [Hardware]
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Virtex 5 HDMI > "maxascent" <maxascent(a)yahoo.co.uk> wrote in message news:HpqdnQS28-7PJwbXnZ2dnUVZ_umdnZ2d(a)giganews.com... Yes I understand what it is but I want some method to use HDMI with a Virtex 5. You could use VHDL or Verilog, or if you know what you are doing schematic capture. hi! wer... 7 Oct 2009 10:44
Very interesting finding about V4 CLB configuration bits The logic function bits (LUT, DFF, MUX ...) for a column of 16 CLBs are in 4 continuous frames (LUT function are in frame 1, 3; DFF bits are in frame 0, 2). I'm make some change in the LUT truth tables (with fpga_editor or ise or whatever) and these changes affect frames 1 and 3. Actually, my logic change will t... 4 Oct 2009 07:43
How to program Spartan 3 Altium nanoboard with Xilinx tools ? Can we program a bitstream in the Daughter Board Spartan 3 of the Altium nanoboard with Xilinx impact instead of Altium Designer ? If yes, which JTAG must be used with which connectors ? I have read interesting stuff on that subject here : http://wiki.altium.com/display/ADOH/Updating+the+Firmware+on+the+Desktop+N... 2 Oct 2009 11:59
SP601 HDL source files available? Hello, in quest for the HDL source files for the Spartan 6 SP601 Demo board and application, all I find is http://forums.xilinx.com/xlnx/board/message?board.id=Spartan&thread.id=3844 BTW, the design files are 'Coming Soon'.... Some zip files are available at http://www.xilinx.com/products/boards/sp601... 3 Nov 2009 09:15
Problem flashing the AT45DB161D on Sparkfun board Hi, I am having the following sparkfun board which has XC3S500E + AT45DB161D on it. http://www.sparkfun.com/commerce/product_info.php?products_id=8458 The FPGA is working (a LED blink bit file works as expected). But when i generate a MCS file (as per xapp974.pdf) to program the config flash, i get various er... 28 Sep 2009 09:11
Problem with using write and write function Hello, I am trying to implement a fir filter in vhdl.. i want to put the output sequence into a text file, so that I can use the same text file in MATLAB and check the frequency response.. The problem I am facing is;;when I try to simulate thro Modelsim, it gives the following errors... # ** Warning: fir_low.vhd(... 29 Sep 2009 01:56
USB programmable Open Source Hardware Looking for interest in an Open Source Hardware USB programmable FPGA, XC3S250E. I have been having some difficulty getting the right people exposed to this project. If you have any interest in this project would like to hear from you. It is headed into an Open Source Hardware agreement therefore their is no propri... 30 Sep 2009 14:38
VHDL question signal next : integer range -1 to 2; function find_first(vector, enable : std_ulogic_vector(0 to 2)) return integer is variable result : integer; begin result := -1; -- omitted calc of first in range of 0..2 return result; end find_first; next <= find_first(val... 23 Sep 2009 17:48
xc3sprog >On Feb 6, 12:45 am, dim...(a)gmail.com wrote: Current version of xc3sprog in SVN incorporates all of the patches submitted so far. I pulled them in a couple of days ago, partially in response to this thread. Please submit your new patches - I will try to keep the project up to date. I... 20 Sep 2009 17:22
82S153 Fuse Map / Disassembler Hi everyone, does anyone on this list have a pointer to a (freely available) JEDEC file disassembler that also supports N82S153 (PLS153) or at least a document showing which bit in the JEDEC file maps to what fuse in the PLS153? Unfortunately, also the N82S153 datasheet on alldatasheets.com doesn't really... 20 Sep 2009 07:21 |