In system memory editor of Altera for Xilinx
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From: Antti on 29 Jan 2010 11:46 On Jan 29, 6:42 pm, Alan Fitch <alan.fi...(a)spamtrap.com> wrote: > austin wrote: > > Antti, > > > Oh, you are so kind! > > > Really, the way to set initial conditions is in your HDL code. > > > For BRAM, there is a whole app note on how to use the data2bram > > utility to set BRAM contents. > > >http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf > > > I would argue that we are (trying to) prevent poor coding practices, > > which lead to errors, and poor HDL code, > > > Austin > > Hi Austin, > isn't that tool called data2mem now? > > regards > Alan > > -- > Alan Fitch > Senior Consultant > > Doulos Developing Design Know-how > VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project > Services > > Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 > 1AW, UK > Tel: + 44 (0)1425 471223 Email: alan.fi...(a)doulos.com > Fax: +44 (0)1425 471573 http://www.doulos.com > > ------------------------------------------------------------------------ > > This message may contain personal views which are not the views of > Doulos, unless specifically stated. its data2mem, it is very useful, but it is NOT THE SAME thing! Altera IDE can edit the memory OVER JTAG, Xilinx tools can not. Antti
From: austin on 29 Jan 2010 12:01 Antti, "If Xilinx cared about the customers...." Cruel, and inappropriate. Of course we care (deeply) about our customers! "Because Xilinx does not have Tool-A, they have no concern for customers..." It would be equally true then to say because the 'other guy' has no domain specific platforms, that they have zero regard for their customers, and force them to re-invent the wheel before they even begin a project ... (which in my humble opinion is all true) So, let us refrain from 'name calling', one could waste a great deal of time, Austin
From: jmunir on 29 Jan 2010 12:06 So, my question is: When I implement a block and I would like to control several of his parameters to test its behaviour, do I have to recompile each time I want to change one of them? :O That has not sense! It is impractical! J. >On Jan 29, 6:42=A0pm, Alan Fitch <alan.fi...(a)spamtrap.com> wrote: >> austin wrote: >> > Antti, >> >> > Oh, you are so kind! >> >> > Really, the way to set initial conditions is in your HDL code. >> >> > For BRAM, there is a whole app note on how to use the data2bram >> > utility to set BRAM contents. >> >> >http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf >> >> > I would argue that we are (trying to) prevent poor coding practices, >> > which lead to errors, and poor HDL code, >> >> > Austin >> >> Hi Austin, >> =A0 =A0isn't that tool called data2mem now? >> >> regards >> Alan >> >> -- >> Alan Fitch >> Senior Consultant >> >> Doulos Developing Design Know-how >> VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project >> Services >> >> Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 >> 1AW, UK >> Tel: =A0+ 44 (0)1425 471223 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Email: alan.fi...= >@doulos.com =A0 =A0 =A0 =A0 >> Fax: =A0+44 (0)1425 471573 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0http://www.doul= >os.com >> >> ------------------------------------------------------------------------ >> >> This message may contain personal views which are not the views of >> Doulos, unless specifically stated. > >its data2mem, it is very useful, but it is NOT THE SAME thing! > >Altera IDE can edit the memory OVER JTAG, >Xilinx tools can not. > >Antti > > > > > > > > > --------------------------------------- Posted through http://www.FPGARelated.com
From: Antti on 29 Jan 2010 12:11 On Jan 29, 7:01 pm, austin <aus...(a)xilinx.com> wrote: > Antti, > > "If Xilinx cared about the customers...." > > Cruel, and inappropriate. > > Of course we care (deeply) about our customers! > > "Because Xilinx does not have Tool-A, they have no concern for > customers..." > > It would be equally true then to say because the 'other guy' has no > domain specific platforms, that they have zero regard for their > customers, and force them to re-invent the wheel before they even > begin a project ... (which in my humble opinion is all true) > > So, let us refrain from 'name calling', one could waste a great deal > of time, > > Austin ah, relax.. both X and A care for the shareholders. but the topic about the "memory editor" is well, it would be SO EASY for Xilinx todo, but it has not been done. some 3rd party could do, i could do it, but it would be much more work for me todo it properly as it would be for xilinx, besides because Xilinx does not open up the xilinx usb cable protocol i could not support xilinx cables from my tool, so it would be pointless todo. there are two reasons why Xilinx does not have memory editor 1) there are some silicon problems, errata, bugs with the silicon preventing the usefulnes of the tool 2) Xilinx just doesnt care to offer this tool I see no other reasons. you can choose. either silicon problems, or lazy programmers. or management issues. i figured out 3rd option. but.. DATA2MEM is MUCH more important (yeah for the customers) then the memory editor and well Altera has no data2mem possibility at all, what is real problem. Xilinx has what is really needed, and misses on optional "good to have" thing that is not that vital. Antti
From: Antti on 29 Jan 2010 12:12
On Jan 29, 7:06 pm, "jmunir" <jmunir(a)n_o_s_p_a_m.gts.tsc.uvigo.es> wrote: > So, my question is: > > When I implement a block and I would like to control several of his > parameters to test its behaviour, do I have to recompile each time I want > to change one of them? :O > > That has not sense! It is impractical! > > J. > NO of course not!!! just use data2mem tool! Antti |