In system memory editor of Altera for Xilinx
in [FPGA]
|
Prev: Thank you, SunMicrosystem
Next: CfP: 9th International Conference on Evolvable Systems (ICES2010)
From: General Schvantzkoph on 29 Jan 2010 12:30 On Fri, 29 Jan 2010 08:13:56 -0800, austin wrote: > Antti, > > Oh, you are so kind! > > Really, the way to set initial conditions is in your HDL code. > > For BRAM, there is a whole app note on how to use the data2bram utility > to set BRAM contents. > > http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf > > I would argue that we are (trying to) prevent poor coding practices, > which lead to errors, and poor HDL code, > > Austin Austin, The ability to change memories or registers has nothing to do with poor coding practices. When you are running a hardware testbench it would be incredibly useful to be able to change the contents of a register in real time rather then having to place and route the design again. Changing a register allows you to be able to select different tests or test conditions. There also ought to be a way to add some signals to ChipScope or SignalTap in a few minutes. The so called quick recompiles aren't quick at all. Speed of adding a few additional signals is an area where both tools are deficient. I use both Xilinx and Altera tools. The place where Xilinx tools are noticeably inferior to Altera's is with ChipScope vs SignalTap. The ChipScope software doesn't even under stand the concept of buses, it requires you to group things together by hand which is a tedious process, SignalTap does this automatically. I wonder if either Xilinx or Altera's tools people bother to look at each others stuff. Chipscope hasn't been improved for years, there is no excuse for it to be as poor as it is, the Xilinx people ought to look at SignalTap and at least match it's features. Just to be even handed about this, the Altera people would benefit from looking at Xilinx's method of doing timing analysis. Altera introduced a new timing tool a couple of years ago and it still sucks. Xilinx produces an easy to read timing report that you can look at in Emacs. It shows the fanout and delays of each stage of the worst case paths, formatted as one line per level. Xilinx also figures out derivative clocks automatically, all you have to do is specify the reference clock speed and the tools automatically figures out the rates and phase relationships of all of the outputs of the PLL or DCM. The Altera tools forces you to do that by hand, what's worse is that you can't even do it using the clock names, you have to figure out the path to the output port of the PLL. Altera's report format is utterly unusable, you are forced to look at worst case paths in the GUI and what it puts out is nearly unreasonable. The bottom line is that I do all of my timing closure using Xilinx tools even if the design is targeted at an Altera part. Once the Xilinx version meets timing I run it through Quartus and hope that I only have a couple of paths that need fixing.
From: Antti on 29 Jan 2010 12:37 On Jan 29, 7:30 pm, General Schvantzkoph <schvantzk...(a)yahoo.com> wrote: > On Fri, 29 Jan 2010 08:13:56 -0800, austin wrote: > > Antti, > > > Oh, you are so kind! > > > Really, the way to set initial conditions is in your HDL code. > > > For BRAM, there is a whole app note on how to use the data2bram utility > > to set BRAM contents. > > >http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf > > > I would argue that we are (trying to) prevent poor coding practices, > > which lead to errors, and poor HDL code, > > > Austin > > Austin, > > The ability to change memories or registers has nothing to do with poor > coding practices. When you are running a hardware testbench it would be > incredibly useful to be able to change the contents of a register in real > time rather then having to place and route the design again. Changing a > register allows you to be able to select different tests or test > conditions. There also ought to be a way to add some signals to ChipScope > or SignalTap in a few minutes. The so called quick recompiles aren't > quick at all. Speed of adding a few additional signals is an area where > both tools are deficient. > > I use both Xilinx and Altera tools. The place where Xilinx tools are > noticeably inferior to Altera's is with ChipScope vs SignalTap. The > ChipScope software doesn't even under stand the concept of buses, it > requires you to group things together by hand which is a tedious process, > SignalTap does this automatically. > > I wonder if either Xilinx or Altera's tools people bother to look at each > others stuff. Chipscope hasn't been improved for years, there is no > excuse for it to be as poor as it is, the Xilinx people ought to look at > SignalTap and at least match it's features. Just to be even handed about > this, the Altera people would benefit from looking at Xilinx's method of > doing timing analysis. Altera introduced a new timing tool a couple of > years ago and it still sucks. Xilinx produces an easy to read timing > report that you can look at in Emacs. It shows the fanout and delays of > each stage of the worst case paths, formatted as one line per level. > Xilinx also figures out derivative clocks automatically, all you have to > do is specify the reference clock speed and the tools automatically > figures out the rates and phase relationships of all of the outputs of > the PLL or DCM. The Altera tools forces you to do that by hand, what's > worse is that you can't even do it using the clock names, you have to > figure out the path to the output port of the PLL. Altera's report format > is utterly unusable, you are forced to look at worst case paths in the > GUI and what it puts out is nearly unreasonable. The bottom line is that > I do all of my timing closure using Xilinx tools even if the design is > targeted at an Altera part. Once the Xilinx version meets timing I run it > through Quartus and hope that I only have a couple of paths that need > fixing. thanks General! yes, both REGISTER (LUT and distributed RAM) as BRAM can be changed via JTAG and ability todo so would be of benefit for Xilinx Customers. As of chipscope hm, it isnt that bad, but it could be better. As of of using X tools, eh I use X tools to make Actel designs..:) I setup Xilinx project, create BRAM modules that look like actel RAM's and then run that on some Xilinx board with Chipscope added to the design. and finally will then replace some modules to target Actel Antti
From: Anssi Saari on 30 Jan 2010 13:38 General Schvantzkoph <schvantzkoph(a)yahoo.com> writes: > The ability to change memories or registers has nothing to do with poor > coding practices. When you are running a hardware testbench it would be > incredibly useful to be able to change the contents of a register in real > time rather then having to place and route the design again. I seem to remember changing BRAM contents with FPGA editor. Should be faster than going through the whole place and route flow.
From: Antti on 30 Jan 2010 14:21 On Jan 30, 8:38 pm, Anssi Saari <a...(a)sci.fi> wrote: > General Schvantzkoph <schvantzk...(a)yahoo.com> writes: > > The ability to change memories or registers has nothing to do with poor > > coding practices. When you are running a hardware testbench it would be > > incredibly useful to be able to change the contents of a register in real > > time rather then having to place and route the design again. > > I seem to remember changing BRAM contents with FPGA editor. Should be > faster than going through the whole place and route flow. well yes you can also sometimes data2mem, but that isnt same things as chaning it over JTAG as it possible with Altera Quartus Antti
From: Walter on 30 Jan 2010 16:04
On 29 ene, 11:22, "jmunir" <jmu...(a)gts.tsc.uvigo.es> wrote: > Hi!, > > I have been working with Altera FPGAs for a long time and now I have to > deal with Xilinx ones. Until now, with Quartus II I have been able to > manage the content of different registers and memories with 'In system > memory editor' and I would like to do the same with Xilinx. I cannot find > the right application to do it. Could you tell me which one I need or how I > can do it? > > Thanx > > J. > > --------------------------------------- > Posted throughhttp://www.FPGARelated.com To debuging proposes you can try JTAG loader, part of KCPSM3 and can be downloaded from Xilinx web site. May be you need do some "bricolage" but work fine. Walter |