In system memory editor of Altera for Xilinx
in [FPGA]
|
Prev: Thank you, SunMicrosystem
Next: CfP: 9th International Conference on Evolvable Systems (ICES2010)
From: Antti on 1 Feb 2010 03:43 On Feb 1, 10:26 am, Goran_Bilski <goran.bil...(a)xilinx.com> wrote: > On Feb 1, 7:36 am, rickman <gnu...(a)gmail.com> wrote: > > > > > > > On Jan 29, 12:06 pm, "jmunir" <jmunir(a)n_o_s_p_a_m.gts.tsc.uvigo.es> > > wrote: > > > > So, my question is: > > > > When I implement a block and I would like to control several of his > > > parameters to test its behaviour, do I have to recompile each time I want > > > to change one of them? :O > > > > That has not sense! It is impractical! > > > > J. > > > I don't think you need to recompile the HDL. You need to produce a > > new bit stream from the original bitstream. Still, this requires a > > number of steps, which can be done in one step with a JTAG tool. > > > Rick > > Hi, > > If you have a design where you want to modify the BRAM contents, > data2mem is the tool to use. > It can modify an existing bitfile and creates a new bitfile with the > new BRAM contents. > After you have created the .bmm file, it's just one call to data2mem > to create a new bitfile with modified BRAM contents. > It takes a few seconds to finish. > > If you just want to toggle some registers down in the target, you can > use Chipscope VIO which allows you to modify signal values in target > using JTAG. > > I agree that it would be good to have a tool that allow you full > control of everything in the device over JTAG but I can also think of > 10+ other tools that would be good to have. > Xilinx doesn't have an infinite number of resources for doing tools > and we have to pick which one we should do. > > One can argue that a comprehensive JTAG debug tool should be one of > them but as today, Xilinx has data2mem and chipscope. > It allows customers accomplish what they want although it might not be > in easiest way for everyone. > > Göran Göran, if-when Xilinx admits it has limited resources, then WHY Xilinx does not allow 3rd party developer to help Xilinx customers? just a small decision to make: open up Xilinx USB Cable API, that is all that Xilinx would have todo. Yes, this also takes resources as it may require some maintenance and code cleanup from Xilinx, but if Xilinx would do that cleanup, it may also be of benefit of Xilinx internal developer team, so at the end Xilinx may actually win saving time not spending it. I would love to re-think and re publish some of my old JTAG tools, but without the ability to talk to Xilinx official USB cables it makes little sense. Altera USB cables are EASY to talk, and there exist 3rd party software that uses them. There is very little 3rd party software supporting completly and without problems Xilinx USB cables. Antti
From: Goran_Bilski on 1 Feb 2010 04:16 On Feb 1, 9:43 am, Antti <antti.luk...(a)googlemail.com> wrote: > On Feb 1, 10:26 am, Goran_Bilski <goran.bil...(a)xilinx.com> wrote: > > > > > > > On Feb 1, 7:36 am, rickman <gnu...(a)gmail.com> wrote: > > > > On Jan 29, 12:06 pm, "jmunir" <jmunir(a)n_o_s_p_a_m.gts.tsc.uvigo.es> > > > wrote: > > > > > So, my question is: > > > > > When I implement a block and I would like to control several of his > > > > parameters to test its behaviour, do I have to recompile each time I want > > > > to change one of them? :O > > > > > That has not sense! It is impractical! > > > > > J. > > > > I don't think you need to recompile the HDL. You need to produce a > > > new bit stream from the original bitstream. Still, this requires a > > > number of steps, which can be done in one step with a JTAG tool. > > > > Rick > > > Hi, > > > If you have a design where you want to modify the BRAM contents, > > data2mem is the tool to use. > > It can modify an existing bitfile and creates a new bitfile with the > > new BRAM contents. > > After you have created the .bmm file, it's just one call to data2mem > > to create a new bitfile with modified BRAM contents. > > It takes a few seconds to finish. > > > If you just want to toggle some registers down in the target, you can > > use Chipscope VIO which allows you to modify signal values in target > > using JTAG. > > > I agree that it would be good to have a tool that allow you full > > control of everything in the device over JTAG but I can also think of > > 10+ other tools that would be good to have. > > Xilinx doesn't have an infinite number of resources for doing tools > > and we have to pick which one we should do. > > > One can argue that a comprehensive JTAG debug tool should be one of > > them but as today, Xilinx has data2mem and chipscope. > > It allows customers accomplish what they want although it might not be > > in easiest way for everyone. > > > Göran > > Göran, > > if-when Xilinx admits it has limited resources, then WHY Xilinx does > not > allow 3rd party developer to help Xilinx customers? > > just a small decision to make: open up Xilinx USB Cable API, that > is all that Xilinx would have todo. Yes, this also takes resources > as it may require some maintenance and code cleanup from Xilinx, > but if Xilinx would do that cleanup, it may also be of benefit of > Xilinx internal developer team, so at the end Xilinx may actually > win saving time not spending it. > > I would love to re-think and re publish some of my old JTAG > tools, but without the ability to talk to Xilinx official USB cables > it makes little sense. > > Altera USB cables are EASY to talk, and there exist 3rd party > software that uses them. There is very little 3rd party software > supporting completly and without problems Xilinx USB cables. > > Antti- Hide quoted text - > > - Show quoted text - Hi Antti, Every company has limited resources so this is not just Xilinx- specific. For this "godly" JTAG debug tool, I doubt that the USB JTAG cable API is the main issue. The tool would need to understand the complete configuration description of every Xilinx architecture and device. The tool also need to support all download cables and not just USB. If this is not about the "godly" JTAG tool but rather that you want to have access to the USB JTAG cable API, I can check if we plan to make it public. I think there is a generic cable API (which should cover all types of download cables, not just USB) but I don't know the status of it. Göran
From: Antti on 1 Feb 2010 04:19 On Feb 1, 11:16 am, Goran_Bilski <goran.bil...(a)xilinx.com> wrote: > On Feb 1, 9:43 am, Antti <antti.luk...(a)googlemail.com> wrote: > > > > > > > On Feb 1, 10:26 am, Goran_Bilski <goran.bil...(a)xilinx.com> wrote: > > > > On Feb 1, 7:36 am, rickman <gnu...(a)gmail.com> wrote: > > > > > On Jan 29, 12:06 pm, "jmunir" <jmunir(a)n_o_s_p_a_m.gts.tsc.uvigo.es> > > > > wrote: > > > > > > So, my question is: > > > > > > When I implement a block and I would like to control several of his > > > > > parameters to test its behaviour, do I have to recompile each time I want > > > > > to change one of them? :O > > > > > > That has not sense! It is impractical! > > > > > > J. > > > > > I don't think you need to recompile the HDL. You need to produce a > > > > new bit stream from the original bitstream. Still, this requires a > > > > number of steps, which can be done in one step with a JTAG tool. > > > > > Rick > > > > Hi, > > > > If you have a design where you want to modify the BRAM contents, > > > data2mem is the tool to use. > > > It can modify an existing bitfile and creates a new bitfile with the > > > new BRAM contents. > > > After you have created the .bmm file, it's just one call to data2mem > > > to create a new bitfile with modified BRAM contents. > > > It takes a few seconds to finish. > > > > If you just want to toggle some registers down in the target, you can > > > use Chipscope VIO which allows you to modify signal values in target > > > using JTAG. > > > > I agree that it would be good to have a tool that allow you full > > > control of everything in the device over JTAG but I can also think of > > > 10+ other tools that would be good to have. > > > Xilinx doesn't have an infinite number of resources for doing tools > > > and we have to pick which one we should do. > > > > One can argue that a comprehensive JTAG debug tool should be one of > > > them but as today, Xilinx has data2mem and chipscope. > > > It allows customers accomplish what they want although it might not be > > > in easiest way for everyone. > > > > Göran > > > Göran, > > > if-when Xilinx admits it has limited resources, then WHY Xilinx does > > not > > allow 3rd party developer to help Xilinx customers? > > > just a small decision to make: open up Xilinx USB Cable API, that > > is all that Xilinx would have todo. Yes, this also takes resources > > as it may require some maintenance and code cleanup from Xilinx, > > but if Xilinx would do that cleanup, it may also be of benefit of > > Xilinx internal developer team, so at the end Xilinx may actually > > win saving time not spending it. > > > I would love to re-think and re publish some of my old JTAG > > tools, but without the ability to talk to Xilinx official USB cables > > it makes little sense. > > > Altera USB cables are EASY to talk, and there exist 3rd party > > software that uses them. There is very little 3rd party software > > supporting completly and without problems Xilinx USB cables. > > > Antti- Hide quoted text - > > > - Show quoted text - > > Hi Antti, > > Every company has limited resources so this is not just Xilinx- > specific. > > For this "godly" JTAG debug tool, I doubt that the USB JTAG cable API > is the main issue. > The tool would need to understand the complete configuration > description of every Xilinx architecture and device. > The tool also need to support all download cables and not just USB. > > If this is not about the "godly" JTAG tool but rather that you want to > have access to the USB JTAG cable API, I can check if we plan to make > it public. > I think there is a generic cable API (which should cover all types of > download cables, not just USB) but I don't know the status of it. > > Göran Xilinx has obsoleted the Parallel port cables, (no longer supported!) so the USB cable is the only cable supported by official tools. right publishing the API, would not "do it all" but it would open possibility for more USEABLE and USEFUL tools to be developed and offered for the Xilinx users. Antti
From: Petter Gustad on 1 Feb 2010 12:48 Goran_Bilski <goran.bilski(a)xilinx.com> writes: > I think there is a generic cable API (which should cover all types of > download cables, not just USB) but I don't know the status of it. What is the URL of this document? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?
From: Antti on 1 Feb 2010 13:03
On Feb 1, 7:48 pm, Petter Gustad <newsmailco...(a)gustad.com> wrote: > Goran_Bilski <goran.bil...(a)xilinx.com> writes: > > I think there is a generic cable API (which should cover all types of > > download cables, not just USB) but I don't know the status of it. > > What is the URL of this document? > > Petter > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail? C:\ its internal Xilinx document. let's pray and hope it eventually comes public in some form Antti |