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From: jmunir on 29 Jan 2010 08:22
Hi!,

I have been working with Altera FPGAs for a long time and now I have to
deal with Xilinx ones. Until now, with Quartus II I have been able to
manage the content of different registers and memories with 'In system
memory editor' and I would like to do the same with Xilinx. I cannot find
the right application to do it. Could you tell me which one I need or how I
can do it?

Thanx

J.



---------------------------------------
Posted through http://www.FPGARelated.com
From: Antti on 29 Jan 2010 09:42
On Jan 29, 3:22 pm, "jmunir" <jmu...(a)gts.tsc.uvigo.es> wrote:
> Hi!,
>
> I have been working with Altera FPGAs for a long time and now I have to
> deal with Xilinx ones. Until now, with Quartus II I have been able to
> manage the content of different registers and memories with 'In system
> memory editor' and I would like to do the same with Xilinx. I cannot find
> the right application to do it. Could you tell me which one I need or how I
> can do it?
>
> Thanx
>
> J.
>
> ---------------------------------------        
> Posted throughhttp://www.FPGARelated.com

there is no such tool for Xilinx
their programmers are just too lazy to make it

Antti

From: austin on 29 Jan 2010 11:13
Antti,

Oh, you are so kind!

Really, the way to set initial conditions is in your HDL code.

For BRAM, there is a whole app note on how to use the data2bram
utility to set BRAM contents.

http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf

I would argue that we are (trying to) prevent poor coding practices,
which lead to errors, and poor HDL code,

Austin
From: Antti on 29 Jan 2010 11:39
On Jan 29, 6:13 pm, austin <aus...(a)xilinx.com> wrote:
> Antti,
>
> Oh, you are so kind!
>
> Really, the way to set initial conditions is in your HDL code.
>
> For BRAM, there is a whole app note on how to use the data2bram
> utility to set BRAM contents.
>
> http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf
>
> I would argue that we are (trying to) prevent poor coding practices,
> which lead to errors, and poor HDL code,
>
> Austin

Austin, I wanted to see the commentary.
and well what I said stands:

Xilinx could implement MEMORY editor the same way as Altera does
suppor it
if Xilinx software guys what care about the customers.

The BRAM's can be accessed over JTAG, this is possible for Altera and
for Xilinx devices
Altera software does allow their customer to edit the BRAM over jtag
because they
have made this software for their customers, and well Xilinx has not.

Antti















From: Alan Fitch on 29 Jan 2010 11:42
austin wrote:
> Antti,
>
> Oh, you are so kind!
>
> Really, the way to set initial conditions is in your HDL code.
>
> For BRAM, there is a whole app note on how to use the data2bram
> utility to set BRAM contents.
>
> http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf
>
> I would argue that we are (trying to) prevent poor coding practices,
> which lead to errors, and poor HDL code,
>
> Austin

Hi Austin,
isn't that tool called data2mem now?

regards
Alan


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