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From: Phil Hobbs on 9 Jul 2010 11:45 On 7/9/2010 10:03 AM, John Larkin wrote: > On Fri, 09 Jul 2010 04:16:27 -0700, > "JosephKK"<quiettechblue(a)yahoo.com> wrote: > >> On Thu, 08 Jul 2010 08:32:12 -0700, John Larkin >> <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >> >>> >>> What path? Understanding bog simple circuits? Stuff like this should >>> be second nature to any electronics designer. It sure shouldn't need >>> to involve cranking up Spice. You use Spice when you *don't* >>> understand how a circuit works. >>> >>> John >>> >> That sounds like a sure fire recipe for getting screwed by SPICE. I have >> watched it happen so very many times. > > Spice is good when the math would be tedious, like simulating > nonlinear control loops, or hairy voltage dividers, or things where > realistic, not simplified, semiconductor behavior must be modeled. Or > when you want to tune a circuit and want to see the possibilities and > have no hard definition of "best." It has to be used carefully, > constantly sanity-checked, because it's easy to make a mistake. Agree, > Spice in the hands of amateurs produces bizarre results. > > Some circuits just aren't understandable in an analytical sense, in > other words are too complex for closed-form solutions or manual > numerical analysis. That's when computers get handy. Different tools > for different problems: Spice, Octave, Matlab, Sonnet, Nuhertz, or > even write your own simulation in PowerBasic or some such. > > We're just finishing up designing a bank of 32 digital IIR lowpass > filters, each 8 poles Bessel or Butterworth, programmable from 100 KHz > to 1 Hz. There's no way to do this analytically... the basic pole/zero > theory is plain enough, but the digital issues are defiant of any > theory we can get our hands on. We're simulating these filters at the > pure math level and again as VHDL, all RAMd/MUXd/DSPblocked/pipelined. > One has to imagine the possible failure modes (overflow, underflow, > limit cycle oscillations, coefficient truncation, whatever) and use > the sim to explore the hazards. > > John > Are you using saturating adders? Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
From: Jim Thompson on 9 Jul 2010 11:47 On Fri, 09 Jul 2010 10:02:22 -0500, John Fields <jfields(a)austininstruments.com> wrote: >On Fri, 09 Jul 2010 07:52:33 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon(a)On-My-Web-Site.com> wrote: > > >>But we wouldn't be bothered by Slowman's rants at all, if certain >>narcissistic jerks didn't keep feeding him. >> >> ...Jim Thompson > >--- >Even I quit! ;) Thanks! Troll feeder filtering is still a nuisance until the next Agent update. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | Obama isn't going to raise your taxes...it's Bush' fault: Not re- newing the Bush tax cuts will increase the bottom tier rate by 50%
From: John Larkin on 9 Jul 2010 12:10 On Fri, 09 Jul 2010 11:45:49 -0400, Phil Hobbs <pcdhSpamMeSenseless(a)electrooptical.net> wrote: >On 7/9/2010 10:03 AM, John Larkin wrote: >> On Fri, 09 Jul 2010 04:16:27 -0700, >> "JosephKK"<quiettechblue(a)yahoo.com> wrote: >> >>> On Thu, 08 Jul 2010 08:32:12 -0700, John Larkin >>> <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>> >>>> >>>> What path? Understanding bog simple circuits? Stuff like this should >>>> be second nature to any electronics designer. It sure shouldn't need >>>> to involve cranking up Spice. You use Spice when you *don't* >>>> understand how a circuit works. >>>> >>>> John >>>> >>> That sounds like a sure fire recipe for getting screwed by SPICE. I have >>> watched it happen so very many times. >> >> Spice is good when the math would be tedious, like simulating >> nonlinear control loops, or hairy voltage dividers, or things where >> realistic, not simplified, semiconductor behavior must be modeled. Or >> when you want to tune a circuit and want to see the possibilities and >> have no hard definition of "best." It has to be used carefully, >> constantly sanity-checked, because it's easy to make a mistake. Agree, >> Spice in the hands of amateurs produces bizarre results. >> >> Some circuits just aren't understandable in an analytical sense, in >> other words are too complex for closed-form solutions or manual >> numerical analysis. That's when computers get handy. Different tools >> for different problems: Spice, Octave, Matlab, Sonnet, Nuhertz, or >> even write your own simulation in PowerBasic or some such. >> >> We're just finishing up designing a bank of 32 digital IIR lowpass >> filters, each 8 poles Bessel or Butterworth, programmable from 100 KHz >> to 1 Hz. There's no way to do this analytically... the basic pole/zero >> theory is plain enough, but the digital issues are defiant of any >> theory we can get our hands on. We're simulating these filters at the >> pure math level and again as VHDL, all RAMd/MUXd/DSPblocked/pipelined. >> One has to imagine the possible failure modes (overflow, underflow, >> limit cycle oscillations, coefficient truncation, whatever) and use >> the sim to explore the hazards. >> >> John >> > >Are you using saturating adders? No. We're using the Xilinx Spartan6 DSP48 blocks mostly, and they don't saturate. We just allow 4 bits of headroom in the 48 bit multiply/accumulate. The front-end ADC calibration is a small offset add and a fractional multiply, so nothing there can go wrong go wrong go wrong. The filters were a bear. I rashly offered 1 Hz through 100 KHz 8-pole Bessel and Butterworth (500 Ks/s ADC rate), one filter per channel, and the customer countered with *two* filters per channel, 32 total on the chip. The coefficients get nasty nasty on both ends. We wound up with 18-bit filter coefficients (to use the 18x18 MAC block, 48 bit accumulator) and a sorta-floating-point shifter in *five* bit steps. It's massively pipelined and interleaved and rather clever; Rob is doing all 32 filters in about 280 slices, down from 6500 in a previous design that just wouldn't fit. All constantly dancing around the oddities and bugs of the Xilinx tools. We also added a post-filter interpolator that lets the user think he's triggering the ADC, when it's actually running at a constant 500 KHz. The user gets, simultaneously, one always-available, filtered "realtime" value of each input, for operator display maybe, and a separate filtered, triggered, FIFOd path for formal data logging. Lotta work. John
From: Phil Hobbs on 9 Jul 2010 12:22 On 7/9/2010 12:10 PM, John Larkin wrote: > On Fri, 09 Jul 2010 11:45:49 -0400, Phil Hobbs > <pcdhSpamMeSenseless(a)electrooptical.net> wrote: > >> On 7/9/2010 10:03 AM, John Larkin wrote: >>> On Fri, 09 Jul 2010 04:16:27 -0700, >>> "JosephKK"<quiettechblue(a)yahoo.com> wrote: >>> >>>> On Thu, 08 Jul 2010 08:32:12 -0700, John Larkin >>>> <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>> >>>>> >>>>> What path? Understanding bog simple circuits? Stuff like this should >>>>> be second nature to any electronics designer. It sure shouldn't need >>>>> to involve cranking up Spice. You use Spice when you *don't* >>>>> understand how a circuit works. >>>>> >>>>> John >>>>> >>>> That sounds like a sure fire recipe for getting screwed by SPICE. I have >>>> watched it happen so very many times. >>> >>> Spice is good when the math would be tedious, like simulating >>> nonlinear control loops, or hairy voltage dividers, or things where >>> realistic, not simplified, semiconductor behavior must be modeled. Or >>> when you want to tune a circuit and want to see the possibilities and >>> have no hard definition of "best." It has to be used carefully, >>> constantly sanity-checked, because it's easy to make a mistake. Agree, >>> Spice in the hands of amateurs produces bizarre results. >>> >>> Some circuits just aren't understandable in an analytical sense, in >>> other words are too complex for closed-form solutions or manual >>> numerical analysis. That's when computers get handy. Different tools >>> for different problems: Spice, Octave, Matlab, Sonnet, Nuhertz, or >>> even write your own simulation in PowerBasic or some such. >>> >>> We're just finishing up designing a bank of 32 digital IIR lowpass >>> filters, each 8 poles Bessel or Butterworth, programmable from 100 KHz >>> to 1 Hz. There's no way to do this analytically... the basic pole/zero >>> theory is plain enough, but the digital issues are defiant of any >>> theory we can get our hands on. We're simulating these filters at the >>> pure math level and again as VHDL, all RAMd/MUXd/DSPblocked/pipelined. >>> One has to imagine the possible failure modes (overflow, underflow, >>> limit cycle oscillations, coefficient truncation, whatever) and use >>> the sim to explore the hazards. >>> >>> John >>> >> >> Are you using saturating adders? > > No. We're using the Xilinx Spartan6 DSP48 blocks mostly, and they > don't saturate. We just allow 4 bits of headroom in the 48 bit > multiply/accumulate. The front-end ADC calibration is a small offset > add and a fractional multiply, so nothing there can go wrong go wrong > go wrong. > > The filters were a bear. I rashly offered 1 Hz through 100 KHz 8-pole > Bessel and Butterworth (500 Ks/s ADC rate), one filter per channel, > and the customer countered with *two* filters per channel, 32 total on > the chip. The coefficients get nasty nasty on both ends. We wound up > with 18-bit filter coefficients (to use the 18x18 MAC block, 48 bit > accumulator) and a sorta-floating-point shifter in *five* bit steps. > It's massively pipelined and interleaved and rather clever; Rob is > doing all 32 filters in about 280 slices, down from 6500 in a previous > design that just wouldn't fit. All constantly dancing around the > oddities and bugs of the Xilinx tools. > > We also added a post-filter interpolator that lets the user think he's > triggering the ADC, when it's actually running at a constant 500 KHz. > The user gets, simultaneously, one always-available, filtered > "realtime" value of each input, for operator display maybe, and a > separate filtered, triggered, FIFOd path for formal data logging. > > Lotta work. > > John > Cute--sounds very useful. I'm a bit leery of fooling the user like that--you might get one who takes that too seriously and winds up with reasonable-looking wrong answers. I just did an ultrahigh precision laser wavelength locker in 100% analog, including the acquisition aid. Took me back, it did, but it was the right method for the situation. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal ElectroOptical Innovations 55 Orchard Rd Briarcliff Manor NY 10510 845-480-2058 hobbs at electrooptical dot net http://electrooptical.net
From: John Larkin on 9 Jul 2010 12:34
On Fri, 09 Jul 2010 12:22:17 -0400, Phil Hobbs <pcdhSpamMeSenseless(a)electrooptical.net> wrote: >On 7/9/2010 12:10 PM, John Larkin wrote: >> On Fri, 09 Jul 2010 11:45:49 -0400, Phil Hobbs >> <pcdhSpamMeSenseless(a)electrooptical.net> wrote: >> >>> On 7/9/2010 10:03 AM, John Larkin wrote: >>>> On Fri, 09 Jul 2010 04:16:27 -0700, >>>> "JosephKK"<quiettechblue(a)yahoo.com> wrote: >>>> >>>>> On Thu, 08 Jul 2010 08:32:12 -0700, John Larkin >>>>> <jjlarkin(a)highNOTlandTHIStechnologyPART.com> wrote: >>>>> >>>>>> >>>>>> What path? Understanding bog simple circuits? Stuff like this should >>>>>> be second nature to any electronics designer. It sure shouldn't need >>>>>> to involve cranking up Spice. You use Spice when you *don't* >>>>>> understand how a circuit works. >>>>>> >>>>>> John >>>>>> >>>>> That sounds like a sure fire recipe for getting screwed by SPICE. I have >>>>> watched it happen so very many times. >>>> >>>> Spice is good when the math would be tedious, like simulating >>>> nonlinear control loops, or hairy voltage dividers, or things where >>>> realistic, not simplified, semiconductor behavior must be modeled. Or >>>> when you want to tune a circuit and want to see the possibilities and >>>> have no hard definition of "best." It has to be used carefully, >>>> constantly sanity-checked, because it's easy to make a mistake. Agree, >>>> Spice in the hands of amateurs produces bizarre results. >>>> >>>> Some circuits just aren't understandable in an analytical sense, in >>>> other words are too complex for closed-form solutions or manual >>>> numerical analysis. That's when computers get handy. Different tools >>>> for different problems: Spice, Octave, Matlab, Sonnet, Nuhertz, or >>>> even write your own simulation in PowerBasic or some such. >>>> >>>> We're just finishing up designing a bank of 32 digital IIR lowpass >>>> filters, each 8 poles Bessel or Butterworth, programmable from 100 KHz >>>> to 1 Hz. There's no way to do this analytically... the basic pole/zero >>>> theory is plain enough, but the digital issues are defiant of any >>>> theory we can get our hands on. We're simulating these filters at the >>>> pure math level and again as VHDL, all RAMd/MUXd/DSPblocked/pipelined. >>>> One has to imagine the possible failure modes (overflow, underflow, >>>> limit cycle oscillations, coefficient truncation, whatever) and use >>>> the sim to explore the hazards. >>>> >>>> John >>>> >>> >>> Are you using saturating adders? >> >> No. We're using the Xilinx Spartan6 DSP48 blocks mostly, and they >> don't saturate. We just allow 4 bits of headroom in the 48 bit >> multiply/accumulate. The front-end ADC calibration is a small offset >> add and a fractional multiply, so nothing there can go wrong go wrong >> go wrong. >> >> The filters were a bear. I rashly offered 1 Hz through 100 KHz 8-pole >> Bessel and Butterworth (500 Ks/s ADC rate), one filter per channel, >> and the customer countered with *two* filters per channel, 32 total on >> the chip. The coefficients get nasty nasty on both ends. We wound up >> with 18-bit filter coefficients (to use the 18x18 MAC block, 48 bit >> accumulator) and a sorta-floating-point shifter in *five* bit steps. >> It's massively pipelined and interleaved and rather clever; Rob is >> doing all 32 filters in about 280 slices, down from 6500 in a previous >> design that just wouldn't fit. All constantly dancing around the >> oddities and bugs of the Xilinx tools. >> >> We also added a post-filter interpolator that lets the user think he's >> triggering the ADC, when it's actually running at a constant 500 KHz. >> The user gets, simultaneously, one always-available, filtered >> "realtime" value of each input, for operator display maybe, and a >> separate filtered, triggered, FIFOd path for formal data logging. >> >> Lotta work. >> >> John >> > >Cute--sounds very useful. I'm a bit leery of fooling the user like >that--you might get one who takes that too seriously and winds up with >reasonable-looking wrong answers. It really ought to work, and act just like a triggered ADC with maybe 10 ns RMS aperature jitter. The only mistake he can make is to trigger at a rate inconsistant with his filter selection, and make aliases, and all we can do about that is warn him in the manual. He's sure not going to get this sort of filter programmability in an old Neff-type analog front-end. > >I just did an ultrahigh precision laser wavelength locker in 100% >analog, including the acquisition aid. Took me back, it did, but it was >the right method for the situation. A couple of fast opamps can outrun 100 watts of DSP. John |