Unified FPGA Development Suite
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From: krw on 10 Oct 2009 20:33 On Sat, 10 Oct 2009 15:20:01 -0700, Jim Thompson <To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >On Sat, 10 Oct 2009 16:59:31 -0500, krw <krw(a)att.bizzzzzzzzzzz> wrote: > >>On Sat, 10 Oct 2009 13:55:34 -0700, Jim Thompson >><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >> >[snip] >>> >>>Clearly I'm not a digital guy... at least beyond pure combinational >>>reduction, which I actually used to teach about 40 years ago. >> >>No one does logic reduction anymore, if they ever did. Gates are >>free. ;-) >> >>>What I'd like is some tool that took in a truth table, each line >>>representing states at that clock tick, spitting out gates, flops, >>>etc., to implement that ;-) >> >>That's easy. Put the table in a ROM and put a counter at the input. >>If you really want to get fancy, put a register at the output. ;-) >> >[snip] > >What I do now (when I don't hand-off the trouble to a buddy) is do >exactly that, counter, plus addressing. > >So-so for simple stuff. Isn't there a better way? I'm not doing >FPGA... I'm doing "gates-on-demand" ;-) The problem with classical minimization is that it requires only a single output. If there is more than one output needed minimization becomes an oxymoron. The question becomes *what* do you want to minimize; gates? delay? skew? power?... Add in library gates more complex than 2I and things get difficult fast. Just the thing for computers to do. ;-) ...and they don't bother with classical minimization either. Back to your question: I have used synthesis tools that will give a "gate view" or "technology view", but they have to be set up for the gate library you're using. The ones I used were specifically for FPGAs but the "gate view" might be useful for you, though the input is still HDL. Answer: no, I don't know of a cheap way of putting me out of work. ;-)
From: Jim Thompson on 10 Oct 2009 20:55 On Sat, 10 Oct 2009 19:33:39 -0500, krw <krw(a)att.bizzzzzzzzzzz> wrote: >On Sat, 10 Oct 2009 15:20:01 -0700, Jim Thompson ><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: > >>On Sat, 10 Oct 2009 16:59:31 -0500, krw <krw(a)att.bizzzzzzzzzzz> wrote: >> >>>On Sat, 10 Oct 2009 13:55:34 -0700, Jim Thompson >>><To-Email-Use-The-Envelope-Icon(a)My-Web-Site.com> wrote: >>> >>[snip] >>>> >>>>Clearly I'm not a digital guy... at least beyond pure combinational >>>>reduction, which I actually used to teach about 40 years ago. >>> >>>No one does logic reduction anymore, if they ever did. Gates are >>>free. ;-) >>> >>>>What I'd like is some tool that took in a truth table, each line >>>>representing states at that clock tick, spitting out gates, flops, >>>>etc., to implement that ;-) >>> >>>That's easy. Put the table in a ROM and put a counter at the input. >>>If you really want to get fancy, put a register at the output. ;-) >>> >>[snip] >> >>What I do now (when I don't hand-off the trouble to a buddy) is do >>exactly that, counter, plus addressing. >> >>So-so for simple stuff. Isn't there a better way? I'm not doing >>FPGA... I'm doing "gates-on-demand" ;-) > >The problem with classical minimization is that it requires only a >single output. If there is more than one output needed minimization >becomes an oxymoron. The question becomes *what* do you want to >minimize; gates? delay? skew? power?... Add in library gates more >complex than 2I and things get difficult fast. Just the thing for >computers to do. ;-) ...and they don't bother with classical >minimization either. > >Back to your question: I have used synthesis tools that will give a >"gate view" or "technology view", but they have to be set up for the >gate library you're using. The ones I used were specifically for >FPGAs but the "gate view" might be useful for you, though the input is >still HDL. Answer: no, I don't know of a cheap way of putting me out >of work. ;-) The process I'm presently designing on (X-FAB XB-06) does have a pre-defined digital library of gates and flops. ...Jim Thompson -- | James E.Thompson, CTO | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona 85048 Skype: Contacts Only | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
From: Peter Bennett on 10 Oct 2009 21:28 On Sat, 10 Oct 2009 17:08:11 -0500, "Jon Slaughter" <Jon_Slaughter(a)Hotmail.com> wrote: >The problem I have is that I brought a few proASIC3's a while ago and I >would like to use them. Unfortunately the libero IDE just crashes on my >system. I can't even get it to a splash screen(which I imagine there is >one). There support is of no help as they just say "Reinstall"(whcih I've >done for various versions). > >Now, it does run under vista in my dual boot configuration but I have all my >tools in XP and never use vista. > >Hence, I would like to be able to develop and debug fgpa code in a working >environment under XP. I can then hop over to vista and "compile" the stuff >in libero when I need the specific device code. > >I know there are tools that do what I want. I think FPGA Advantage does >it... or did it. A book called fpga warrior mentions some linux tools(I >have). > >Basically I just need something to get started writing some code so I can >get my head wrapped around how it all works(I have an idea but I need to get >some experience). I prefer to work in a C++ like language since I'm more >familiar with it and oop is more powerful for complex designs. I think linux >has a SystemC compiler. I do have Cygwin installed so might be able to use >some of the tools there. I don't think C++ can be used to configure an FPGA. (I prefer the term "configure", rather than "program" to describe what we do to an FPGA, although I do use "program" to describe downloading the configuration file to the FPGA.) FPGAs and CPLDs consist of a large number of gates, flip-flops and other devices that the user can connect together as desires, to perform some useful function. I've used Altera's Quartus program to generate configuration files for their FPGAs and CPLDs. Quartus allows me to design the circuit either by drawing schematic diagrams using gates, flip-flops, and other logic elements, or by using a Hardware Description Language (AHDL or VHDL) to describe the required logic in a text file (or to use both schematic and AHDL in the same project.) It is possible to include a processor in the FPGA configuration - then that processor could be programmed, like any other processor, using C or C++ (if you can find a suitable cross-compiler.) However, the FPGA configuration and processor program development are two separate steps. -- Peter Bennett, VE7CEI peterbb4 (at) interchange.ubc.ca GPS and NMEA info: http://vancouver-webpages.com/peter Vancouver Power Squadron: http://vancouver.powersquadron.ca
From: osr on 10 Oct 2009 21:32 For the div boards: fpga4fun.com ? Steve
From: David L. Jones on 10 Oct 2009 21:50
Jon Slaughter wrote: > "Jon Slaughter" <Jon_Slaughter(a)Hotmail.com> wrote in message > news:haoqug$35j$1(a)news.eternal-september.org... >> Is there a development suite that is good but can target multiple >> fpga manufactures? I don't really want to install a bunch of 1GB+ >> light versions >> for each manufacture just to see which one is best. In fact I can't >> even get >> libero to run because it crashes on startup. >> >> Also, know of any links for DIY fpga programmers? How hard is it to >> program? I figured that one just has to feed a bitstream into the >> fpga similar to how a pic is programmed(or most devices actually). >> Looking at the proASIC's makes me think it's a bit different but I >> haven't found any conclusive way to program them except by using >> DirectC or the STAPL Player. >> Since I'm experimenting with these different manufactures I don't >> want to have to buy a programmer for each chip. For as much as they >> cost I could get >> nanoboard with 10^10x the functionality. > > BTW, I forgot to mention that I want to program in C++. Pure C++ but > SystemC or similar if necessary. Altium have a Xilinx (others on the way) development board and 12 month license of their full soft package for $399 http://www.newark.com/altium/12-400-nb3000xn-01/nanoboard-3000xn-xilinx-spartan/dp/10R0248 For that you get C and C++, VHDL/Verilog, GUI like OpenBus, Real-time OS, and/or C to Hardware compiler for your development. Plus 32bit processors and other IP. No restrictions. Altium uses the Xilinx (or other) tools as the back-end, but it's all seamless, you don't notice you are using them. If you do want to experiment with different manufactuers, the Nanoboard NB2 is better, but it's $2K. They have a JTAG programmer for $150 for use on your own custom boards: http://www.newark.com/altium/12-403-dt01/usb-jtag-adapter/dp/10R0257 Dave. -- --------------------------------------------- Check out my Electronics Engineering Video Blog & Podcast: http://www.eevblog.com |