synthesizing a completely empty design for an FPGA to measure quiescent current
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From: rickman on 29 Jan 2010 14:35 On Jan 29, 1:42 pm, Antti <antti.luk...(a)googlemail.com> wrote: > On Jan 29, 8:38 pm, Ed McGettigan <ed.mcgetti...(a)xilinx.com> wrote: > > > > > On Jan 29, 10:21 am, Gabor <ga...(a)alacron.com> wrote: > > > > On Jan 29, 12:50 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > > > > On Jan 29, 7:47 pm, EE EE <eengr....(a)gmail.com> wrote: > > > > > > Hi > > > > > I want to synthesize a completely empty design, no clocks no combo and > > > > > no sequential logic for a xilinx FPGA using ISE. > > > > > THe problem is > > > > > if I try to implement module dummy_fpga (); endmodule > > > > > The tool synthesizes it but fails to translate it. > > > > > I wanted to create an empty design with no inputs and no outputs and > > > > > then use bit gen to float all unused IOs. This was I could measure the > > > > > quiescent current of the xilinx FPGA. > > > > > Any suggestions? > > > > > Thanks > > > > > you do have to have one output or the flow will fail > > > > > well, design with no IO's could actually be useful, if all data > > > > transfer goes over BSCAN, but the tools require one top level port to > > > > be present > > > > > Antti > > > > It would seem to me that pulling the PROG_B pin low would put the > > > device into as quiescent state as you can get. But as for a post- > > > programmed state I don't think driving at least one I/O would change > > > the quiescent current significantly vs "no design". > > > > Regards, > > > Gabor- Hide quoted text - > > > > - Show quoted text - > > > That won't work as when PROG_B is pulled low this starts house > > cleaning activities and the current will spike (from quiescient) > > > One input and Output with no toggling activities = Quiescient power. > > > Ed McGettigan > > -- > > Xilinx Inc. > > why the input?? If your output can not be traced back to an input, it will be optimized away. You could drive the output with a constant value, so the actual input pin is not needed, but the output has to be driven by something. But as you have discovered, this is a tool issue, not a fundamental issue with the design process. So the tools might just require an input, but I doubt it. Rick
From: Andy on 29 Jan 2010 15:16 One output, driven from a constant, should be all you need. Just make sure your one output is not driving a load in your test/ measurement setup. And make sure your IO pins are not pulled down (internal pullups are enabled on unused pins) Andy
From: Ed McGettigan on 29 Jan 2010 19:05 On Jan 29, 10:42 am, Antti <antti.luk...(a)googlemail.com> wrote: > On Jan 29, 8:38 pm, Ed McGettigan <ed.mcgetti...(a)xilinx.com> wrote: > > > > > > > On Jan 29, 10:21 am, Gabor <ga...(a)alacron.com> wrote: > > > > On Jan 29, 12:50 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > > > > On Jan 29, 7:47 pm, EE EE <eengr....(a)gmail.com> wrote: > > > > > > Hi > > > > > I want to synthesize a completely empty design, no clocks no combo and > > > > > no sequential logic for a xilinx FPGA using ISE. > > > > > THe problem is > > > > > if I try to implement module dummy_fpga (); endmodule > > > > > The tool synthesizes it but fails to translate it. > > > > > I wanted to create an empty design with no inputs and no outputs and > > > > > then use bit gen to float all unused IOs. This was I could measure the > > > > > quiescent current of the xilinx FPGA. > > > > > Any suggestions? > > > > > Thanks > > > > > you do have to have one output or the flow will fail > > > > > well, design with no IO's could actually be useful, if all data > > > > transfer goes over BSCAN, but the tools require one top level port to > > > > be present > > > > > Antti > > > > It would seem to me that pulling the PROG_B pin low would put the > > > device into as quiescent state as you can get. But as for a post- > > > programmed state I don't think driving at least one I/O would change > > > the quiescent current significantly vs "no design". > > > > Regards, > > > Gabor- Hide quoted text - > > > > - Show quoted text - > > > That won't work as when PROG_B is pulled low this starts house > > cleaning activities and the current will spike (from quiescient) > > > One input and Output with no toggling activities = Quiescient power. > > > Ed McGettigan > > -- > > Xilinx Inc. > > why the input??- Hide quoted text - > > - Show quoted text - Why not? I find it simpler that way since design of A=B always works. Ed McGettigan -- Xilinx
From: -jg on 29 Jan 2010 21:57 On Jan 30, 6:47 am, EE EE <eengr....(a)gmail.com> wrote: > Hi > I want to synthesize a completely empty design, no clocks no combo and > no sequential logic for a xilinx FPGA using ISE. > THe problem is > if I try to implement module dummy_fpga (); endmodule > The tool synthesizes it but fails to translate it. > I wanted to create an empty design with no inputs and no outputs and > then use bit gen to float all unused IOs. This was I could measure the > quiescent current of the xilinx FPGA. > Any suggestions? > Thanks As others have said, o=i is a tool-happy minimum. You might want to be more intelligent with test patterns tho, and try some pins that allow Hi or Low by IO bank. I have seen one programmable device, where the state of buried nodes was measurable on Icc, so design your test to catch the unexpected.... -jg
From: Antti on 30 Jan 2010 01:07
On Jan 30, 2:05 am, Ed McGettigan <ed.mcgetti...(a)xilinx.com> wrote: > On Jan 29, 10:42 am, Antti <antti.luk...(a)googlemail.com> wrote: > > > > > > > On Jan 29, 8:38 pm, Ed McGettigan <ed.mcgetti...(a)xilinx.com> wrote: > > > > On Jan 29, 10:21 am, Gabor <ga...(a)alacron.com> wrote: > > > > > On Jan 29, 12:50 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > > > > > On Jan 29, 7:47 pm, EE EE <eengr....(a)gmail.com> wrote: > > > > > > > Hi > > > > > > I want to synthesize a completely empty design, no clocks no combo and > > > > > > no sequential logic for a xilinx FPGA using ISE. > > > > > > THe problem is > > > > > > if I try to implement module dummy_fpga (); endmodule > > > > > > The tool synthesizes it but fails to translate it. > > > > > > I wanted to create an empty design with no inputs and no outputs and > > > > > > then use bit gen to float all unused IOs. This was I could measure the > > > > > > quiescent current of the xilinx FPGA. > > > > > > Any suggestions? > > > > > > Thanks > > > > > > you do have to have one output or the flow will fail > > > > > > well, design with no IO's could actually be useful, if all data > > > > > transfer goes over BSCAN, but the tools require one top level port to > > > > > be present > > > > > > Antti > > > > > It would seem to me that pulling the PROG_B pin low would put the > > > > device into as quiescent state as you can get. But as for a post- > > > > programmed state I don't think driving at least one I/O would change > > > > the quiescent current significantly vs "no design". > > > > > Regards, > > > > Gabor- Hide quoted text - > > > > > - Show quoted text - > > > > That won't work as when PROG_B is pulled low this starts house > > > cleaning activities and the current will spike (from quiescient) > > > > One input and Output with no toggling activities = Quiescient power.. > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > why the input??- Hide quoted text - > > > - Show quoted text - > > Why not? I find it simpler that way since design of A=B always works.. > > Ed McGettigan > -- > Xilinx TOO COMPLICATED! LED <= '1'; is simpler as only one output pin is needed, it is the dummy design i use. |