synthesizing a completely empty design for an FPGA to measure quiescent current
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From: -jg on 30 Jan 2010 16:25 On Jan 30, 10:41 pm, Antti <antti.luk...(a)googlemail.com> wrote: > On Jan 30, 11:18 am, -jg <jim.granvi...(a)gmail.com> wrote: > > > > > On Jan 30, 9:59 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > > > On Jan 30, 10:57 am, -jg <jim.granvi...(a)gmail.com> wrote: > > > > > On Jan 30, 7:08 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > > > > > o=i; > > > > > > is not needed > > > > > > o='1'; > > > > > > is sufficient > > > > > but Sufficient to test only the o=1 case, > > > > by making the OP under user control, you can test > > > > both H and L outputs with one compile ;) > > > > -jg > > > > Jim, it was not about TESTING the output, it was about creating an > > > EMPTY design. > > > there is no need to test anything with empty design :) > > > > Antti > > > The OP wanted to "measure the quiescent current of the xilinx FPGA", > > and that can vary with H & L, > > so the best test coverage is to check both. > > > He probably should also plot Icc vs Vin on a pin, so he can factor in > > non-cmos or level shifting effects, if needed. > > > -jg > > nono, he did not want measure the current in dependancy of the output > being driven high or low, in the matter of fact he would have > preffered the output to not be driven at all, so actually he should > have made a desing that is as small as possible, and has one output > that is always tristated. Hehe, if his REAL system is going to have no outputs driven, then you would be correct. However, in the real world, a vital part of "measuring the quiescent current" of a static system is to have the I/O lines at 'field likely' states. ie On my bench, I want to know if the pin state, or even Vi level, mattered. On many chips, it does. If you ignore this stuff, it can bite you! I'll admit I presumed the OP wanted a useful number. -jg
From: Krzysztof Kepa on 31 Jan 2010 09:24 Why not use XDL? 1.Get any ncd file targeting your x device and convert it to xdl format ('xdl -ncd2xdl anydesign.ncd') 2.copy the first (uncommented) line from the xdl file (contains target device name) to a new file (e.g. empty.xdl) 3. convert the new xdl file back to ncd format ('xdl -xdl2ncd -force empty_design.xdl empty_design.ncd') 4. create bit file ('bitgen -d empty_design.ncd') 4.profit :) You could also use below python script Regards, Krzysztof empty_design.py : import os xdl_content = '< put here first line from the xdl file with target device>' empty_file = open("empty_design.xdl",'w') empty_file.write(xdl_content) empty_file.close() os.system("xdl -xdl2ncd -force empty_design.xdl empty_design.ncd") os.system("bitgen -d empty_design.ncd") "EE EE" <eengr.usa(a)gmail.com> wrote in message news:27dcf723-c9ad-4f45-b9f2-ec1b2d4268a2(a)x1g2000prb.googlegroups.com... > Hi > I want to synthesize a completely empty design, no clocks no combo and > no sequential logic for a xilinx FPGA using ISE. > THe problem is > if I try to implement module dummy_fpga (); endmodule > The tool synthesizes it but fails to translate it. > I wanted to create an empty design with no inputs and no outputs and > then use bit gen to float all unused IOs. This was I could measure the > quiescent current of the xilinx FPGA. > Any suggestions? > Thanks
From: saar drimer on 3 Feb 2010 11:50 On Jan 29, 5:47 pm, EE EE <eengr....(a)gmail.com> wrote: > I want to synthesize a completely empty design, no clocks no combo and > no sequential logic for a xilinx FPGA using ISE. Would the following satisfy your requirements? 1. open a new design in fpga_editor (chose your part, etc.) and save it to empty.ncd 2. bitgen empty.ncd ....you then get an "empty" bitstream, empty.bit. saar.
From: Kolja Sulimma on 4 Feb 2010 05:20 On 29 Jan., 18:50, Antti <antti.luk...(a)googlemail.com> wrote: > On Jan 29, 7:47 pm, EE EE <eengr....(a)gmail.com> wrote: > you do have to have one output or the flow will fail > > well, design with no IO's could actually be useful, if all data > transfer goes over BSCAN, but the tools require one top level port to > be present Also, a design with only inputs can be used to use DCI to terminate external signals which might be required for external circuitry to work properly. Kolja Sulimma
From: Kolja Sulimma on 4 Feb 2010 05:22
On 29 Jan., 20:35, rickman <gnu...(a)gmail.com> wrote: > So the tools might just > require an input, but I doubt it. This used to be the case a few years ago. The bug has been fixed, but might have been reintroduces later. Designs with only outputs did not work in an earlier ISE version but I had a real world application with only a single output. (An CPLD had to hold OE of a flash at constant high, in a later version there would be logic added to the CPLD, but that was not read yet) Translate failed with the error mesage similar to: Does not fit, your design has 0 inputs but the CPLD you have chosen has only 32 Pins. I opened a web case to research a design that will provide a constant output without the tool optimizing away the dummy input. You could not synthesize output <= '1'; in that version. Kolja Sulimma |