synthesizing a completely empty design for an FPGA to measure quiescent current
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From: EE EE on 29 Jan 2010 12:47 Hi I want to synthesize a completely empty design, no clocks no combo and no sequential logic for a xilinx FPGA using ISE. THe problem is if I try to implement module dummy_fpga (); endmodule The tool synthesizes it but fails to translate it. I wanted to create an empty design with no inputs and no outputs and then use bit gen to float all unused IOs. This was I could measure the quiescent current of the xilinx FPGA. Any suggestions? Thanks
From: Antti on 29 Jan 2010 12:50 On Jan 29, 7:47 pm, EE EE <eengr....(a)gmail.com> wrote: > Hi > I want to synthesize a completely empty design, no clocks no combo and > no sequential logic for a xilinx FPGA using ISE. > THe problem is > if I try to implement module dummy_fpga (); endmodule > The tool synthesizes it but fails to translate it. > I wanted to create an empty design with no inputs and no outputs and > then use bit gen to float all unused IOs. This was I could measure the > quiescent current of the xilinx FPGA. > Any suggestions? > Thanks you do have to have one output or the flow will fail well, design with no IO's could actually be useful, if all data transfer goes over BSCAN, but the tools require one top level port to be present Antti
From: Gabor on 29 Jan 2010 13:21 On Jan 29, 12:50 pm, Antti <antti.luk...(a)googlemail.com> wrote: > On Jan 29, 7:47 pm, EE EE <eengr....(a)gmail.com> wrote: > > > Hi > > I want to synthesize a completely empty design, no clocks no combo and > > no sequential logic for a xilinx FPGA using ISE. > > THe problem is > > if I try to implement module dummy_fpga (); endmodule > > The tool synthesizes it but fails to translate it. > > I wanted to create an empty design with no inputs and no outputs and > > then use bit gen to float all unused IOs. This was I could measure the > > quiescent current of the xilinx FPGA. > > Any suggestions? > > Thanks > > you do have to have one output or the flow will fail > > well, design with no IO's could actually be useful, if all data > transfer goes over BSCAN, but the tools require one top level port to > be present > > Antti It would seem to me that pulling the PROG_B pin low would put the device into as quiescent state as you can get. But as for a post- programmed state I don't think driving at least one I/O would change the quiescent current significantly vs "no design". Regards, Gabor
From: Ed McGettigan on 29 Jan 2010 13:38 On Jan 29, 10:21 am, Gabor <ga...(a)alacron.com> wrote: > On Jan 29, 12:50 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > > > > > > On Jan 29, 7:47 pm, EE EE <eengr....(a)gmail.com> wrote: > > > > Hi > > > I want to synthesize a completely empty design, no clocks no combo and > > > no sequential logic for a xilinx FPGA using ISE. > > > THe problem is > > > if I try to implement module dummy_fpga (); endmodule > > > The tool synthesizes it but fails to translate it. > > > I wanted to create an empty design with no inputs and no outputs and > > > then use bit gen to float all unused IOs. This was I could measure the > > > quiescent current of the xilinx FPGA. > > > Any suggestions? > > > Thanks > > > you do have to have one output or the flow will fail > > > well, design with no IO's could actually be useful, if all data > > transfer goes over BSCAN, but the tools require one top level port to > > be present > > > Antti > > It would seem to me that pulling the PROG_B pin low would put the > device into as quiescent state as you can get. But as for a post- > programmed state I don't think driving at least one I/O would change > the quiescent current significantly vs "no design". > > Regards, > Gabor- Hide quoted text - > > - Show quoted text - That won't work as when PROG_B is pulled low this starts house cleaning activities and the current will spike (from quiescient) One input and Output with no toggling activities = Quiescient power. Ed McGettigan -- Xilinx Inc.
From: Antti on 29 Jan 2010 13:42
On Jan 29, 8:38 pm, Ed McGettigan <ed.mcgetti...(a)xilinx.com> wrote: > On Jan 29, 10:21 am, Gabor <ga...(a)alacron.com> wrote: > > > > > > > On Jan 29, 12:50 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > > > On Jan 29, 7:47 pm, EE EE <eengr....(a)gmail.com> wrote: > > > > > Hi > > > > I want to synthesize a completely empty design, no clocks no combo and > > > > no sequential logic for a xilinx FPGA using ISE. > > > > THe problem is > > > > if I try to implement module dummy_fpga (); endmodule > > > > The tool synthesizes it but fails to translate it. > > > > I wanted to create an empty design with no inputs and no outputs and > > > > then use bit gen to float all unused IOs. This was I could measure the > > > > quiescent current of the xilinx FPGA. > > > > Any suggestions? > > > > Thanks > > > > you do have to have one output or the flow will fail > > > > well, design with no IO's could actually be useful, if all data > > > transfer goes over BSCAN, but the tools require one top level port to > > > be present > > > > Antti > > > It would seem to me that pulling the PROG_B pin low would put the > > device into as quiescent state as you can get. But as for a post- > > programmed state I don't think driving at least one I/O would change > > the quiescent current significantly vs "no design". > > > Regards, > > Gabor- Hide quoted text - > > > - Show quoted text - > > That won't work as when PROG_B is pulled low this starts house > cleaning activities and the current will spike (from quiescient) > > One input and Output with no toggling activities = Quiescient power. > > Ed McGettigan > -- > Xilinx Inc. why the input?? |