synthesizing a completely empty design for an FPGA to measure quiescent current
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From: Antti on 30 Jan 2010 01:08 On Jan 30, 4:57 am, -jg <jim.granvi...(a)gmail.com> wrote: > On Jan 30, 6:47 am, EE EE <eengr....(a)gmail.com> wrote: > > > Hi > > I want to synthesize a completely empty design, no clocks no combo and > > no sequential logic for a xilinx FPGA using ISE. > > THe problem is > > if I try to implement module dummy_fpga (); endmodule > > The tool synthesizes it but fails to translate it. > > I wanted to create an empty design with no inputs and no outputs and > > then use bit gen to float all unused IOs. This was I could measure the > > quiescent current of the xilinx FPGA. > > Any suggestions? > > Thanks > > As others have said, o=i is a tool-happy minimum. > > You might want to be more intelligent with test patterns tho, and try > some pins that allow Hi or Low by IO bank. > > I have seen one programmable device, where the state of buried nodes > was measurable on Icc, so design your test to catch the unexpected.... > -jg o=i; is not needed o='1'; is sufficient Antti
From: -jg on 30 Jan 2010 03:57 On Jan 30, 7:08 pm, Antti <antti.luk...(a)googlemail.com> wrote: > o=i; > > is not needed > > o='1'; > > is sufficient but Sufficient to test only the o=1 case, by making the OP under user control, you can test both H and L outputs with one compile ;) -jg
From: Antti on 30 Jan 2010 03:59 On Jan 30, 10:57 am, -jg <jim.granvi...(a)gmail.com> wrote: > On Jan 30, 7:08 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > > o=i; > > > is not needed > > > o='1'; > > > is sufficient > > but Sufficient to test only the o=1 case, > by making the OP under user control, you can test > both H and L outputs with one compile ;) > -jg Jim, it was not about TESTING the output, it was about creating an EMPTY design. there is no need to test anything with empty design :) Antti
From: -jg on 30 Jan 2010 04:18 On Jan 30, 9:59 pm, Antti <antti.luk...(a)googlemail.com> wrote: > On Jan 30, 10:57 am, -jg <jim.granvi...(a)gmail.com> wrote: > > > On Jan 30, 7:08 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > > > o=i; > > > > is not needed > > > > o='1'; > > > > is sufficient > > > but Sufficient to test only the o=1 case, > > by making the OP under user control, you can test > > both H and L outputs with one compile ;) > > -jg > > Jim, it was not about TESTING the output, it was about creating an > EMPTY design. > there is no need to test anything with empty design :) > > Antti The OP wanted to "measure the quiescent current of the xilinx FPGA", and that can vary with H & L, so the best test coverage is to check both. He probably should also plot Icc vs Vin on a pin, so he can factor in non-cmos or level shifting effects, if needed. -jg
From: Antti on 30 Jan 2010 04:41
On Jan 30, 11:18 am, -jg <jim.granvi...(a)gmail.com> wrote: > On Jan 30, 9:59 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > > > > > > On Jan 30, 10:57 am, -jg <jim.granvi...(a)gmail.com> wrote: > > > > On Jan 30, 7:08 pm, Antti <antti.luk...(a)googlemail.com> wrote: > > > > > o=i; > > > > > is not needed > > > > > o='1'; > > > > > is sufficient > > > > but Sufficient to test only the o=1 case, > > > by making the OP under user control, you can test > > > both H and L outputs with one compile ;) > > > -jg > > > Jim, it was not about TESTING the output, it was about creating an > > EMPTY design. > > there is no need to test anything with empty design :) > > > Antti > > The OP wanted to "measure the quiescent current of the xilinx FPGA", > and that can vary with H & L, > so the best test coverage is to check both. > > He probably should also plot Icc vs Vin on a pin, so he can factor in > non-cmos or level shifting effects, if needed. > > -jg nono, he did not want measure the current in dependancy of the output being driven high or low, in the matter of fact he would have preffered the output to not be driven at all, so actually he should have made a desing that is as small as possible, and has one output that is always tristated. Antti |