FPGA

Spartan 6 MCB arcitecture
Hi all, I'm new in DDR2, I've read the MIG document UG388 but I don't quite understand, I'm wondering if anyones could explain me about the performance of the MCB's internal write/read FIFO datapath? the DDR2 is 16bits wide, and I need one 64bits write port and one 64bits read port for my implementation, the data... 23 Jul 2010 12:30

WTB: Xilinx USB JTAG Cable
On Jul 22, 1:12 am, Tim Wescott <t...(a)seemywebsite.com> wrote: According to Avnet, Xilinx is out of their USB JTAG cables for weeks. I need one (see post about Linux, Cables, woe, etc.). Anyone got one?  Anyone close to Oregon City, Oregon got one?  I'm willing to pay a fair price, particularly if it'... 22 Jul 2010 05:55

Using std_ulogic at synthesis level
Dear everybody, in the following piece of code ... if sRxOld /= iRx then if vHIGH >= T_500ns then sBit <= 'U'; elsif vLOW >= T_500ns then sBit <= 'U'; ... 24 Jul 2010 10:09

Xilinx Plan Ahead question
Hi, I' m new to Plan Ahead 12.1 and I' ve some values of I/O Ports in red color. It concerns DDR3 pins and values in red are Drive Strength (12*) and Slew Type (SLOW*). What could be the signification? Thanks ... 22 Jul 2010 12:29

WTB: Xilinx USB JTAG Cable
According to Avnet, Xilinx is out of their USB JTAG cables for weeks. I need one (see post about Linux, Cables, woe, etc.). Anyone got one? Anyone close to Oregon City, Oregon got one? I'm willing to pay a fair price, particularly if it's within driving distance. -- Tim Wescott Wescott Design Services... 23 Jul 2010 13:36

Parallel Cable IV under Ubuntu Linux 10.04
Is there any way to do this? Is there any way to do this without standing on my head? The last time I used ISE this was a Windows box. But I've evolved into a Higher Life Form*, and now I don't do Windows if I can help it**. I'd sidestep the whole problem by getting a USB JTAG cable and running Windows in... 24 Jul 2010 08:00

How to create a LVPECL_25 output pair (Spartan3, ISE 9.1)
I'm trying to create a LVPECL_25 differential output on a Spartan 3 (XC3S200 device in PQ208 package). I did this by selecting 'LVPECL_25' in the I/O Standard column in PACE (assign package pins). However, in 'Implement Design' I get the following error: Process "Translate" completed successfully Using target... 22 Jul 2010 03:46

Announcing AjarDSP - an open source VLIW DSP
Hi all, This is a post to announce the existence of the AjarDSP project, an attempt to design and implement an open source VLIW DSP with an open source tool chain (assembler, simulator/debugger and C compiler). Check out the details at: http://code.google.com/p/ajardsp/ regards Markus ... 28 Jul 2010 19:33

Xilinx' partition flow in ISE12.1
Hey Sean, Sorry for the late post and my guess is you have either given up or figured out how to do this. Unroutes should not be happening by just adding Partitions. If you want to try again, you might want to look at the number of INFO and WARNING messages about constants on inputs and/or outputs and also the... 20 Jul 2010 14:39

Last Call for Papers Reminder (extended): International Conference on Soft Computing and Applications ICSCA 2010
Last Call for Papers Reminder (extended): International Conference on Soft Computing and Applications ICSCA 2010 CFP (extended): International Conference on Soft Computing and Applications ICSCA 2010 Draft Paper Submission Deadline (extended): 26 July, 2010 Camera-Ready Papers Due & Registration Deadline (extend... 20 Jul 2010 10:13