FPGA

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Virtex 4 FX12 minimodule
Hi all Has any one used Virtex 4 FX12 minimodule along with any ADC(analog to digital converter) IC for sending digitiized data on ethernet? If someone has any experience on FX12 mini module kindly share it. THANKS --------------------------------------- Posted through http://www.FPGARelat... 19 Jul 2010 08:02

Xilinx License BS
Welcome to the club. Xilinx is not alone on this. A long time ago, I saw a study on quality of software. 90% of problems were with licensing. Better luck next time. Pete ... 20 Jul 2010 04:50

I2C Master Start stop generation
Hi All I am implementing an I2C slave and low level interface to interface it to EEPROM. I am using I2c Master for verifying this module . The I2C Master code is reused from some other module. He has implemented the I2C in a fashion that the PULL up and the Pull Down is to be provided from outside. It has SCL_IN... 19 Jul 2010 13:32

Ariadne Designs Ltd
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Cortex-M1 in Actel in strait VHDL?
Hello All, I have a requirement to build a SOC design with two Arm cores along with some standard and custom peripherals. The Actel Cortex-M1 enabled FPGA's appear to be ideal for my application because the licensing fee is included in the price of the processor. I have started playing around with the Libero ... 24 Jul 2010 12:18

Dumb VHDL Question -- Type Conversion
How do I assign an integer value to 'signed' or 'unsigned' from the IEEE libraries? I'm having this difficulty with my test benches. Surely there's a set of library functions to do it, but I can't seem to figure out what they are!! -- Tim Wescott Wescott Design Services http://www.wescottdesign.com ... 23 Jul 2010 20:12

Drigmorn4 - Spartan-6 Board
Our third product based on Spartan-6 is Drigmorn4 http://www.enterpoint.co.uk/drigmorn/drigmorn4.html and it is now available in very limited quantities. It's very much of the same concept as Drigmorn3 but with the benefit of a bigger Spartan-6 FPGA - XC6SLX45 through to XC6SLX150. We also support bitstream encrypt... 16 Jul 2010 20:56

Timing analysis of asynchronous bus peripherals
Hello everyone, I have a (maybe) simple problem I don't know exactly how to face up. I am given a design (which is made by a third person) that realizes simple bus peripherals upon a Altera CPLD. The design is quite simple: the address bus along with the data bus and the READ signals are brought as inputs of the C... 16 Jul 2010 07:42